[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] edcc4e: target/riscv: machine: Sort the .subs
From: |
Richard Henderson |
Subject: |
[Qemu-commits] [qemu/qemu] edcc4e: target/riscv: machine: Sort the .subsections |
Date: |
Wed, 17 Nov 2021 01:52:16 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: edcc4e4090ac56ea0d85ec482dd77bd7cc009b70
https://github.com/qemu/qemu/commit/edcc4e4090ac56ea0d85ec482dd77bd7cc009b70
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-11-17 (Wed, 17 Nov 2021)
Changed paths:
M target/riscv/machine.c
Log Message:
-----------
target/riscv: machine: Sort the .subsections
Move the codes around so that the order of .subsections matches
the one they are referenced in vmstate_riscv_cpu.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211030030606.32297-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c94c239496256f1f1cb589825d052c2f3e26ebf6
https://github.com/qemu/qemu/commit/c94c239496256f1f1cb589825d052c2f3e26ebf6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-11-17 (Wed, 17 Nov 2021)
Changed paths:
M meson.build
Log Message:
-----------
meson.build: Merge riscv32 and riscv64 cpu family
In ba0e73336200, we merged riscv32 and riscv64 in configure.
However, meson does not treat them the same. We need to merge
them here as well.
Fixes: ba0e73336200
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211116095042.335224-1-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 52cebbfc133fb784644edeae1e5b53aac3b64e5f
https://github.com/qemu/qemu/commit/52cebbfc133fb784644edeae1e5b53aac3b64e5f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-11-17 (Wed, 17 Nov 2021)
Changed paths:
M meson.build
M target/riscv/machine.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20211117-1' of github.com:alistair23/qemu into
staging
Sixth RISC-V PR for QEMU 6.2
- Fix build for riscv hosts
- Soft code alphabetically
# gpg: Signature made Wed 17 Nov 2021 10:19:25 AM CET
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
* tag 'pull-riscv-to-apply-20211117-1' of github.com:alistair23/qemu:
meson.build: Merge riscv32 and riscv64 cpu family
target/riscv: machine: Sort the .subsections
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/8d5fcb1990bc...52cebbfc133f
- [Qemu-commits] [qemu/qemu] edcc4e: target/riscv: machine: Sort the .subsections,
Richard Henderson <=