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[Qemu-commits] [qemu/qemu] 9c33e0: target/riscv: Avoid env_archcpu() whe
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 9c33e0: target/riscv: Avoid env_archcpu() when reading RIS... |
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Date: |
Fri, 05 May 2023 01:26:25 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 9c33e08b2bcff481310665b89d05ecf232174ebc
https://github.com/qemu/qemu/commit/9c33e08b2bcff481310665b89d05ecf232174ebc
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 662ed9cc850bd20fe06f5c0488e0b5701997ac54
https://github.com/qemu/qemu/commit/662ed9cc850bd20fe06f5c0488e0b5701997ac54
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Fix priv version dependency for vector and zfh
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector
only requires PRIV_1_10_0, these sub extensions should not require priv version
higher than that.
The same for Zfh.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230321043415.754-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 99c2f5c42ad7d5084c28d16890425ca2d339e9ef
https://github.com/qemu/qemu/commit/99c2f5c42ad7d5084c28d16890425ca2d339e9ef
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/pmu.c
Log Message:
-----------
target/riscv: Simplify getting RISCVCPU pointer from env
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230309071329.45932-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bbb9fc2591cdecfa40ba7791101e91c83441ed49
https://github.com/qemu/qemu/commit/bbb9fc2591cdecfa40ba7791101e91c83441ed49
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/pmu.c
M target/riscv/time_helper.c
M target/riscv/time_helper.h
Log Message:
-----------
target/riscv: Simplify type conversion for CPURISCVState
Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCVCPU in many caller of them and then back to CPURISCVState in them.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d53ae79b2895218c03a1e5e5c83049567215ab2e
https://github.com/qemu/qemu/commit/d53ae79b2895218c03a1e5e5c83049567215ab2e
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Simplify arguments for riscv_csrrw_check
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230309071329.45932-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 378e43fa722a501fbf94f81fa89a87a7a78dddcb
https://github.com/qemu/qemu/commit/378e43fa722a501fbf94f81fa89a87a7a78dddcb
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvzicond.c.inc
Log Message:
-----------
target/riscv: refactor Zicond support
After the original Zicond support was stuck/fell through the cracks on
the mailing list at v3 (and a different implementation was merged in
the meanwhile), we need to refactor Zicond to prepare it to be reused
by XVentanaCondOps.
This commit lifts the common logic out into gen_czero and uses this
via gen_logic and 2 helper functions (effectively partial closures).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307180708.302867-2-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4f2493146d783d71c5dc6e72452f80b86641ba7f
https://github.com/qemu/qemu/commit/4f2493146d783d71c5dc6e72452f80b86641ba7f
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M MAINTAINERS
M target/riscv/insn_trans/trans_xventanacondops.c.inc
Log Message:
-----------
target/riscv: redirect XVentanaCondOps to use the Zicond functions
The Zicond standard extension implements the same instruction
semantics as XVentanaCondOps, although using different mnemonics and
opcodes.
Point XVentanaCondOps to the (newly implemented) Zicond implementation
to reduce the future maintenance burden.
Also updating MAINTAINERS as trans_xventanacondops.c.inc.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307180708.302867-3-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 48249c023d4fd7931f65cd13341cdef1c72bab45
https://github.com/qemu/qemu/commit/48249c023d4fd7931f65cd13341cdef1c72bab45
Author: Conor Dooley <conor.dooley@microchip.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/pmu.c
Log Message:
-----------
target/riscv: fix invalid riscv,event-to-mhpmcounters entry
dt-validate complains:
> soc: pmu: {'riscv,event-to-mhpmcounters':
> [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280],
> [65563, 65563, 524280], [65569, 65569, 524280], [0, 0, 0], [0, 0]],
> pmu: riscv,event-to-mhpmcounters:6: [0, 0] is too short
There are bogus 0 entries added at the end, of which one is of
insufficient length. This happens because only 15 of
fdt_event_ctr_map[]'s 20 elements are populated & qemu_fdt_setprop() is
called using the size of the array.
Reduce the array to 15 elements to make the error go away.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230404173333.35179-1-conor@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2288a5ce43e54ff883cd193f0a8bd91c420e4771
https://github.com/qemu/qemu/commit/2288a5ce43e54ff883cd193f0a8bd91c420e4771
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: add cfg properties for Zc* extension
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension.
Add check for these properties.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b17dd74a5433dcdb3baa63e9eb968d35df60b85a
https://github.com/qemu/qemu/commit/b17dd74a5433dcdb3baa63e9eb968d35df60b85a
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: add support for Zca extension
Modify the check for C extension to Zca (C implies Zca).
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20230307081403.61950-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 30b03579020db497ef328101e8c51cb6752a9c2e
https://github.com/qemu/qemu/commit/30b03579020db497ef328101e8c51cb6752a9c2e
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/insn16.decode
M target/riscv/insn_trans/trans_rvf.c.inc
Log Message:
-----------
target/riscv: add support for Zcf extension
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c4935b58422d4692bae6f37069a5cbb748656b29
https://github.com/qemu/qemu/commit/c4935b58422d4692bae6f37069a5cbb748656b29
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/insn16.decode
M target/riscv/insn_trans/trans_rvd.c.inc
Log Message:
-----------
target/riscv: add support for Zcd extension
Separate c_fld/c_fsd from fld/fsd to add additional check for
c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
their encodings.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e0a3054f18e20602768d328b0cb7d5910253a327
https://github.com/qemu/qemu/commit/e0a3054f18e20602768d328b0cb7d5910253a327
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/insn16.decode
A target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: add support for Zcb extension
Add encode and trans* functions support for Zcb instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 193eb522e4083d8e84c3fae443fd98bc300b95d0
https://github.com/qemu/qemu/commit/193eb522e4083d8e84c3fae443fd98bc300b95d0
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/insn16.decode
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: add support for Zcmp extension
Add encode, trans* functions for Zcmp instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ce3af0bbbcdfa754cd50f278e83a750730a67c25
https://github.com/qemu/qemu/commit/ce3af0bbbcdfa754cd50f278e83a750730a67c25
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/csr.c
M target/riscv/helper.h
M target/riscv/insn16.decode
M target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/machine.c
M target/riscv/meson.build
A target/riscv/zce_helper.c
Log Message:
-----------
target/riscv: add support for Zcmt extension
Add encode, trans* functions and helper functions support for Zcmt
instrutions.
Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d364c0ab68796aea3608e73ccbaa635dd55a38fc
https://github.com/qemu/qemu/commit/d364c0ab68796aea3608e73ccbaa635dd55a38fc
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: expose properties for Zc* extension
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-9-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2c71d02e17771f58ce4d89ca71b756fb3ecf9525
https://github.com/qemu/qemu/commit/2c71d02e17771f58ce4d89ca71b756fb3ecf9525
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv.c: add disasm support for Zc*
Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd*
instructions currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-10-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 00d312bd78c91650e05b6e9676650db6865576f0
https://github.com/qemu/qemu/commit/00d312bd78c91650e05b6e9676650db6865576f0
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Add support for Zce
Add and expose property for Zce:
* Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt.
* Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: df3ac6da476e346a17bad5bc843de1135a269229
https://github.com/qemu/qemu/commit/df3ac6da476e346a17bad5bc843de1135a269229
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/insn_trans/trans_privileged.c.inc
Log Message:
-----------
target/riscv: Fix itrigger when icount is used
When I boot a ubuntu image, QEMU output a "Bad icount read" message and exit.
The reason is that when execute helper_mret or helper_sret, it will
cause a call to icount_get_raw_locked (), which needs set can_do_io flag
on cpustate.
Thus we setting this flag when execute these two instructions.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230324064011.976-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2136b6c30c0f0a4653163dd2f72a01a96ad778d2
https://github.com/qemu/qemu/commit/2136b6c30c0f0a4653163dd2f72a01a96ad778d2
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Remove redundant call to riscv_cpu_virt_enabled
The assignment is done under the condition riscv_cpu_virt_enabled()=true.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230327080858.39703-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fbec3f382af5c1746d7ff803e88daf92175f4c24
https://github.com/qemu/qemu/commit/fbec3f382af5c1746d7ff803e88daf92175f4c24
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Remove redundant check on RVH
Check on riscv_cpu_virt_enabled contains the check on RVH.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230327080858.39703-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 286629216c72f76d8871e57c1abbd0252ebb29ba
https://github.com/qemu/qemu/commit/286629216c72f76d8871e57c1abbd0252ebb29ba
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
Since env->virt.VIRT_ONOFF is initialized as false, and will not be set
to true when RVH is disabled, so we can just return this bit(false) when
RVH is not disabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230327080858.39703-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c43732f505a8094449704db2bb5f08ee3fd60350
https://github.com/qemu/qemu/commit/c43732f505a8094449704db2bb5f08ee3fd60350
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
In current implementation, riscv_cpu_set_virt_enabled is only called when
RVH is enabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230327080858.39703-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b3c5077befaebf2281515f36ddbf482f3e0818aa
https://github.com/qemu/qemu/commit/b3c5077befaebf2281515f36ddbf482f3e0818aa
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/machine.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Convert env->virt to a bool env->virt_enabled
Currently we only use the env->virt to encode the virtual mode enabled
status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230325145348.1208-1-zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230327080858.39703-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 628f0ec1ed631594395bda5e79aaf3e4bd641b6e
https://github.com/qemu/qemu/commit/628f0ec1ed631594395bda5e79aaf3e4bd641b6e
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Remove redundant parentheses
Remove redundant parentheses in get_physical_address.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230327080858.39703-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 77dff6509c5655fe959acf7a6d4fe923b6f292b8
https://github.com/qemu/qemu/commit/77dff6509c5655fe959acf7a6d4fe923b6f292b8
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Fix addr type for get_physical_address
Function get_physical_address() translates both virtual address and
guest physical address, and the latter is 34-bits for Sv32x4. So we
should use vaddr type for 'addr' parameter.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230329101928.83856-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 22c2f87ab2e5c2a57e4a2ab2a02e89fe4dad608a
https://github.com/qemu/qemu/commit/22c2f87ab2e5c2a57e4a2ab2a02e89fe4dad608a
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvh.c.inc
Log Message:
-----------
target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 38256529f39189753100954f9c8ea94eaa95144b
https://github.com/qemu/qemu/commit/38256529f39189753100954f9c8ea94eaa95144b
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/debug.c
M target/riscv/op_helper.c
M target/riscv/pmu.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Remove riscv_cpu_virt_enabled()
Directly use env->virt_enabled instead.
Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230405085813.40643-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c45eff30cb5be9906b879b641a4b4e6d47f3f860
https://github.com/qemu/qemu/commit/c45eff30cb5be9906b879b641a4b4e6d47f3f860
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/arch_dump.c
M target/riscv/cpu.c
M target/riscv/cpu_helper.c
M target/riscv/fpu_helper.c
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/m128_helper.c
M target/riscv/machine.c
M target/riscv/op_helper.c
M target/riscv/pmp.c
M target/riscv/pmp.h
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix format for indentation
Fix identation problems, and try to use the same indentation strategy
in the same file.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3b57254d8a61497e21bfbe635c7a2dba4ece12dc
https://github.com/qemu/qemu/commit/3b57254d8a61497e21bfbe635c7a2dba4ece12dc
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/arch_dump.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/pmp.c
M target/riscv/sbi_ecall_interface.h
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix format for comments
Fix formats for multi-lines comments.
Add spaces around single line comments(after "/*" and before "*/").
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230405085813.40643-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 246f87960a22d293ab4033bdfee3d4258494ec9b
https://github.com/qemu/qemu/commit/246f87960a22d293ab4033bdfee3d4258494ec9b
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/debug.c
M target/riscv/gdbstub.c
M target/riscv/pmp.c
M target/riscv/pmu.c
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix lines with over 80 characters
Fix lines with over 80 characters for both code and comments.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 66247edc8b6fb36d6b905babcd795068ea989ad5
https://github.com/qemu/qemu/commit/66247edc8b6fb36d6b905babcd795068ea989ad5
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M hw/char/riscv_htif.c
M hw/riscv/spike.c
M include/hw/char/riscv_htif.h
Log Message:
-----------
hw/riscv: Add signature dump function for spike to run ACT tests
Add signature and signature-granularity properties in spike to specify the
target
signatrue file and the line size for signature data.
Recgonize the signature section between begin_signature and end_signature
symbols
when loading elf of ACT tests. Then dump signature data in signature section
just
before the ACT tests exit.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230405095720.75848-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1ffa805c9d07bf1059d11a183540a3f07d02ea11
https://github.com/qemu/qemu/commit/1ffa805c9d07bf1059d11a183540a3f07d02ea11
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: sync env->misa_ext* with cpu->cfg in realize()
When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N
properties updated. The same can't be said about env->misa_ext*, since
the user might enable/disable MISA extensions in the command line, and
env->misa_ext* won't caught these changes. The current solution is to
sync everything at the end of validate_set_extensions(), checking every
cpu->cfg.ext_N value to do a set_misa() in the end.
The last change we're making in the MISA cfg flags are in the G
extension logic, enabling IMAFG if cpu->cfg_ext.g is enabled. Otherwise
we're not making any changes in MISA bits ever since realize() starts.
There's no reason to postpone misa_ext updates until the end of the
validation. Let's do it earlier, during realize(), in a new helper
called riscv_cpu_sync_misa_cfg(). If cpu->cfg.ext_g is enabled, do it
again by updating env->misa_ext* directly.
This is a pre-requisite to allow riscv_cpu_validate_set_extensions() to
use riscv_has_ext() instead of cpu->cfg.ext_N to validate the MISA
extensions, which is our end goal here.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6508272a8a92c46f0c1161466bc607ea6aea302d
https://github.com/qemu/qemu/commit/6508272a8a92c46f0c1161466bc607ea6aea302d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: remove MISA properties from isa_edata_arr[]
The code that disables extensions if there's a priv version mismatch
uses cpu->cfg.ext_N properties to do its job.
We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
the MISA related verifications in a new function, removing it from
isa_edata_arr[].
We're also erroring it out instead of disabling, making the cpu_init()
function responsible for running an adequate priv spec for the MISA
extensions it wants to use.
Note that the RVV verification is being ignored since we're always have
at least PRIV_VERSION_1_10_0.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ccc84a7588aa8b0ac61d9b8e60364bd1919cc7b7
https://github.com/qemu/qemu/commit/ccc84a7588aa8b0ac61d9b8e60364bd1919cc7b7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
We don't have MISA extensions in isa_edata_arr[] anymore. Remove the
redundant 'multi_letter' field from isa_ext_data.
Suggested-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b3df64c89bd18b81e7689b8e26ef940e9a7ff078
https://github.com/qemu/qemu/commit/b3df64c89bd18b81e7689b8e26ef940e9a7ff078
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: introduce riscv_cpu_add_misa_properties()
Ever since RISCVCPUConfig got introduced users are able to set CPU extensions
in the command line. User settings are reflected in the cpu->cfg object
for later use. These properties are used in the target/riscv/cpu.c code,
most notably in riscv_cpu_validate_set_extensions(), where most of our
realize time validations are made.
And then there's env->misa_ext, the field where the MISA extensions are
set, that is read everywhere else. We need to keep env->misa_ext updated
with cpu->cfg settings, since our validations rely on it, forcing us to
make register_cpu_props() write cpu->cfg.ext_N flags to cover for named
CPUs that aren't used named properties but also needs to go through the
same validation steps. Failing to so will make those name CPUs fail
validation (see c66ffcd5358b for more info). Not only that, but we also
need to sync env->misa_ext with cpu->cfg again during realize() time to
catch any change the user might have done, since the rest of the code
relies on that.
Making cpu->cfg.ext_N and env->misa_ext reflect each other is not
needed. What we want is a way for users to enable/disable MISA extensions,
and there's nothing stopping us from letting the user write env->misa_ext
directly. Here are the artifacts that will enable us to do that:
- RISCVCPUMisaExtConfig will declare each MISA property;
- cpu_set_misa_ext_cfg() is the setter for each property. We'll write
env->misa_ext and env->misa_ext_mask with the appropriate misa_bit;
cutting off cpu->cfg.ext_N from the logic;
- cpu_get_misa_ext_cfg() is a getter that will retrieve the current val
of the property based on env->misa_ext;
- riscv_cpu_add_misa_properties() will be called in register_cpu_props()
to init all MISA properties from the misa_ext_cfgs[] array.
With this infrastructure we'll start to get rid of each cpu->cfg.ext_N
attribute in the next patches.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4c759943ec23bca891ad25fb2a9988f1b78f9e7d
https://github.com/qemu/qemu/commit/4c759943ec23bca891ad25fb2a9988f1b78f9e7d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_a
Create a new "a" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are
replaced with riscv_has_ext(env, RVA).
Remove the old "a" property and 'ext_a' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c00226e1f0620fda90c985631b31afe2a87f7e97
https://github.com/qemu/qemu/commit/c00226e1f0620fda90c985631b31afe2a87f7e97
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_c
Create a new "c" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are
replaced with riscv_has_ext(env, RVC).
Remove the old "c" property and 'ext_c' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ffffd954ba168d5b6812d25b8cf49d160874f241
https://github.com/qemu/qemu/commit/ffffd954ba168d5b6812d25b8cf49d160874f241
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_d
Create a new "d" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
replaced with riscv_has_ext(env, RVD).
Remove the old "d" property and 'ext_d' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4b33598fbe8cd899a08e7ac1cff9b9cb1e8477e9
https://github.com/qemu/qemu/commit/4b33598fbe8cd899a08e7ac1cff9b9cb1e8477e9
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_f
Create a new "f" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are
replaced with riscv_has_ext(env, RVF).
Remove the old "f" property and 'ext_f' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 74828eabf2c301ff93fee297519d25e0f1804b2a
https://github.com/qemu/qemu/commit/74828eabf2c301ff93fee297519d25e0f1804b2a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_i
Create a new "i" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are
replaced with riscv_has_ext(env, RVI).
Remove the old "i" property and 'ext_i' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 427d8e7dd871a747727dbbfef22041fedef2ee32
https://github.com/qemu/qemu/commit/427d8e7dd871a747727dbbfef22041fedef2ee32
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/insn_trans/trans_rvzce.c.inc
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_e
Create a new "e" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are
replaced with riscv_has_ext(env, RVE).
Remove the old "e" property and 'ext_e' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1a36e23a62283ecca1b56a983cfce67e4ec84ee7
https://github.com/qemu/qemu/commit/1a36e23a62283ecca1b56a983cfce67e4ec84ee7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_m
Create a new "m" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are
replaced with riscv_has_ext(env, RVM).
Remove the old "m" property and 'ext_m' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f1ea2a52dc298f4ffa589c7ae25c1204aec1b5f1
https://github.com/qemu/qemu/commit/f1ea2a52dc298f4ffa589c7ae25c1204aec1b5f1
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_s
Create a new "s" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are
replaced with riscv_has_ext(env, RVS).
Remove the old "s" property and 'ext_s' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e17801e1708da60371550af5a67e14c7d8db4eae
https://github.com/qemu/qemu/commit/e17801e1708da60371550af5a67e14c7d8db4eae
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_u
Create a new "u" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are
replaced with riscv_has_ext(env, RVU).
Remove the old "u" property and 'ext_u' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b5c042e8a0300989b7e9ce0d24b6535c77439d3e
https://github.com/qemu/qemu/commit/b5c042e8a0300989b7e9ce0d24b6535c77439d3e
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_h
Create a new "h" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are
replaced with riscv_has_ext(env, RVH).
Remove the old "h" property and 'ext_h' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 64f4b541c52d3ea581e9123b5bab8b915323e76d
https://github.com/qemu/qemu/commit/64f4b541c52d3ea581e9123b5bab8b915323e76d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_j
Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3e7674fd1ab1f04b811629123190b80fea15e41d
https://github.com/qemu/qemu/commit/3e7674fd1ab1f04b811629123190b80fea15e41d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: remove cpu->cfg.ext_v
Create a new "v" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are
replaced with riscv_has_ext(env, RVV).
Remove the old "v" property and 'ext_v' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7295b18606602c6b0b841a0f089db7f01b6c7ec1
https://github.com/qemu/qemu/commit/7295b18606602c6b0b841a0f089db7f01b6c7ec1
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: remove riscv_cpu_sync_misa_cfg()
This function was created to move the sync between cpu->cfg.ext_N bit
changes to env->misa_ext* from the validation step to an ealier step,
giving us a guarantee that we could use either cpu->cfg.ext_N or
riscv_has_ext(env,N) in the validation.
We don't have any cpu->cfg.ext_N left that has an existing MISA bit
(cfg.ext_g will be handled shortly). The function is now a no-op, simply
copying the existing values of misa_ext* back to misa_ext*.
Remove it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8ef67c663709f5a7d3be239777e65479ac236d23
https://github.com/qemu/qemu/commit/8ef67c663709f5a7d3be239777e65479ac236d23
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
This CPU is enabling G via cfg.ext_g and, at the same time, setting
IMAFD in set_misa() and cfg.ext_icsr.
riscv_cpu_validate_set_extensions() is already doing that, so there's no
need for cpu_init() setups to worry about setting G and its extensions.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4f13abcb2bcba47692cc3a171fda61dc46fc89be
https://github.com/qemu/qemu/commit/4f13abcb2bcba47692cc3a171fda61dc46fc89be
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: add RVG and remove cpu->cfg.ext_g
We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it
the same way we did with the others: create a "g" RISCVCPUMisaExtConfig
property, remove the old "g" property, remove all instances of 'cfg.ext_g'
and use riscv_has_ext(env, RVG).
The caveat is that we don't have RVG, so add it. RVG will be used right
off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is
enabling G via the now removed 'ext_g' flag.
After this patch, there are no more MISA extensions represented by flags
in RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: dd8f244f353391952a1e1147afad92dc78fb97ed
https://github.com/qemu/qemu/commit/dd8f244f353391952a1e1147afad92dc78fb97ed
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv/cpu.c: redesign register_cpu_props()
The function is now a no-op for all cpu_init() callers that are setting
a non-zero misa value in set_misa(), since it's no longer used to sync
cpu->cfg props with env->misa_ext bits. Remove it in those cases.
While we're at it, rename the function to match what it's actually
doing: create user properties to set/remove CPU extensions. Make a note
that it will overwrite env->misa_ext with the defaults set by each user
property.
Update the MISA bits comment in cpu.h as well.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-21-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 04803c3ddb37a8c84392452c3596bd1c4474904d
https://github.com/qemu/qemu/commit/04803c3ddb37a8c84392452c3596bd1c4474904d
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Fix the mstatus.MPP value after executing MRET
The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230407014743.18779-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 44b8f74b0088df22f30e0718f6aefa9fb87702f6
https://github.com/qemu/qemu/commit/44b8f74b0088df22f30e0718f6aefa9fb87702f6
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/gdbstub.c
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Use PRV_RESERVED instead of PRV_H
PRV_H has no real meaning, but just a reserved privilege mode currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230407014743.18779-3-liweiwei@iscas.ac.cn>
[ Changes by AF:
- Convert one missing use of PRV_H
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0c98ccef49b015b5625495b451315a06a54525ec
https://github.com/qemu/qemu/commit/0c98ccef49b015b5625495b451315a06a54525ec
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Legalize MPP value in write_mstatus
mstatus.MPP field is a WARL field since priv version 1.11, so we
remain it unchanged if an invalid value is written into it. And
after this, RVH shouldn't be passed to riscv_cpu_set_mode().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230407014743.18779-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9ba63f9442067729c3fe41c88b1eb414874d46ea
https://github.com/qemu/qemu/commit/9ba63f9442067729c3fe41c88b1eb414874d46ea
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx
Zdinx/Zhinx{min} require Zfinx. And require relationship is usually done
by check currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230408135908.25269-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d6db7c975e2e0d60850043ea8f208dd446a61d0a
https://github.com/qemu/qemu/commit/d6db7c975e2e0d60850043ea8f208dd446a61d0a
Author: Yi Chen <chenyi2000@zju.edu.cn>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/csr.c
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: fix H extension TVM trap
- Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
- Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
- Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
- Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes
SFENCE.VMA/SINVAL.VMA or VS-mode executes SFENCE.VMA/SINVAL.VMA with
HSTATUS.VTVM enabled.
- Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes
HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA.
Signed-off-by: Yi Chen <chenyi2000@zju.edu.cn>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406101559.39632-1-chenyi2000@zju.edu.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f196639024fb460b7f5bbee39215b90b58810788
https://github.com/qemu/qemu/commit/f196639024fb460b7f5bbee39215b90b58810788
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Extract virt enabled state from tb flags
Virt enabled state is not a constant, so we should put it into tb flags.
Thus we can use it like a constant condition at translation phase.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-2-zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-2-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 42967f40731c197cb8e59ad8ac480a2dcc80c199
https://github.com/qemu/qemu/commit/42967f40731c197cb8e59ad8ac480a2dcc80c199
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Add a general status enum for extensions
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com>
[rth: Add a typedef for the enum]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ebd476488d1369d602534e82234d410ca1734f07
https://github.com/qemu/qemu/commit/ebd476488d1369d602534e82234d410ca1734f07
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Encode the FS and VS on a normal way for tb flags
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a
normal way.
It will make it hard to change the tb flags layout. And even worse, if we
want to keep tb flags for a same extension togather without a hole.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com>
[rth: Adjust trans_rvf.c.inc as well; use the typedef]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 25f3ddff5f57610b22abfa1cd5808653a92e5265
https://github.com/qemu/qemu/commit/25f3ddff5f57610b22abfa1cd5808653a92e5265
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
Merge with mstatus_{fs,vs}. We might perform a redundant
assignment to one or the other field, but it's a trivial
and saves 4 bits from TB_FLAGS.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-5-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-5-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4acaa133b1f7af1867ac9e98bacc75012e6c123a
https://github.com/qemu/qemu/commit/4acaa133b1f7af1867ac9e98bacc75012e6c123a
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add a tb flags field for vstart
Once we mistook the vstart directly from the env->vstart. As env->vstart is not
a constant, we should record it in the tb flags if we want to use
it in translation.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-5-zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-6-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-6-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 47debc7280430cc7665af2cb70caa1a4325ca060
https://github.com/qemu/qemu/commit/47debc7280430cc7665af2cb70caa1a4325ca060
Author: Fei Wu <fei2.wu@intel.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/insn_trans/trans_privileged.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Separate priv from mmu_idx
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx. Here an
individual priv field is added into TB_FLAGS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fei Wu <fei2.wu@intel.com>
Message-Id: <20230324054154.414846-2-fei2.wu@intel.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c8f8a9957ea20ac4ba0588ddd00130e8dcf41d93
https://github.com/qemu/qemu/commit/c8f8a9957ea20ac4ba0588ddd00130e8dcf41d93
Author: Fei Wu <fei2.wu@intel.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/insn_trans/trans_rvh.c.inc
M target/riscv/internals.h
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Reduce overhead of MSTATUS_SUM change
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.
This patch creates a separate MMU index for S+SUM, so that it's not
necessary to flush tlb anymore when SUM changes. This is similar to how
ARM handles Privileged Access Never (PAN).
Result of 'pipe 10' from unixbench boosts from 223656 to 1705006. Many
other syscalls benefit a lot from this too.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fei Wu <fei2.wu@intel.com>
Message-Id: <20230324054154.414846-3-fei2.wu@intel.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-8-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-8-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a7f112c5fd1ac22732e523c8e933728fca681a0a
https://github.com/qemu/qemu/commit/a7f112c5fd1ac22732e523c8e933728fca681a0a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Use cpu_ld*_code_mmu for HLVX
Use the new functions to properly check execute permission
for the read rather than read permission.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-10-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-10-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0f58cbbeea4a6c7f8b14f09cc18acfbb3a00e2e9
https://github.com/qemu/qemu/commit/0f58cbbeea4a6c7f8b14f09cc18acfbb3a00e2e9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/helper.h
M target/riscv/insn_trans/trans_rvh.c.inc
M target/riscv/op_helper.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Handle HLV, HSV via helpers
Implement these instructions via helpers, in expectation
of determining the mmu_idx to use at runtime. This allows
the permission check to also be moved out of line, which
allows HLSX to be removed from TB_FLAGS.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-11-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-11-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3df44173e9f4de3d39e784020991cd0424c4074e
https://github.com/qemu/qemu/commit/3df44173e9f4de3d39e784020991cd0424c4074e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/internals.h
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
We will enable more uses of this bit in the future.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4005a799f190e8c07afa45c88b1b45a9df00ee92
https://github.com/qemu/qemu/commit/4005a799f190e8c07afa45c88b1b45a9df00ee92
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/internals.h
Log Message:
-----------
target/riscv: Introduce mmuidx_sum
In get_physical_address, we should use the setting passed
via mmu_idx rather than checking env->mstatus directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-13-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-13-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 340b5805dbf42c0cb26eaa64d069bf3b43ee4f55
https://github.com/qemu/qemu/commit/340b5805dbf42c0cb26eaa64d069bf3b43ee4f55
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/internals.h
Log Message:
-----------
target/riscv: Introduce mmuidx_priv
Use the priv level encoded into the mmu_idx, rather than
starting from env->priv. We have already checked MPRV+MPP
in riscv_cpu_mmu_index -- no need to repeat that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 02369f790676f8118b8f0769f58d5890e15fcd25
https://github.com/qemu/qemu/commit/02369f790676f8118b8f0769f58d5890e15fcd25
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/internals.h
Log Message:
-----------
target/riscv: Introduce mmuidx_2stage
Move and rename riscv_cpu_two_stage_lookup, to match
the other mmuidx_* functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-15-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9de7b7b5c7ca8e81c6d62b7c5c5a4753fa597bcb
https://github.com/qemu/qemu/commit/9de7b7b5c7ca8e81c6d62b7c5c5a4753fa597bcb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Move hstatus.spvp check to check_access_hlsv
The current cpu_mmu_index value is really irrelevant to
the HLV/HSV lookup. Provide the correct priv level directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 696bacde957bc5cdabc7710abc316ef56184d928
https://github.com/qemu/qemu/commit/696bacde957bc5cdabc7710abc316ef56184d928
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
Incorporate the virt_enabled and MPV checks into the cpu_mmu_index
function, so we don't have to keep doing it within tlb_fill and
subroutines. This also elides a flush on changes to MPV.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-17-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-17-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: eaecd473ca0e91c59dcf8a9e58b32518ed6b1bdf
https://github.com/qemu/qemu/commit/eaecd473ca0e91c59dcf8a9e58b32518ed6b1bdf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Check SUM in the correct register
Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level
vsstatus.SUM instead of HS-level sstatus.SUM.
For HLV/HSV instructions, the HS-level register does not apply, but
the VS-level register presumably does, though this is not mentioned
explicitly in the manual. However, it matches the behavior for MPV.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-18-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-18-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a427c83633924d2bc9485d30c2658dd9fc44b9f1
https://github.com/qemu/qemu/commit/a427c83633924d2bc9485d30c2658dd9fc44b9f1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Hoist second stage mode change to callers
Move the check from the top of get_physical_address to
the two callers, where passing mmu_idx makes no sense.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-19-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8d6a00cdc01b912acceb9a03e77ad86fb7954b17
https://github.com/qemu/qemu/commit/8d6a00cdc01b912acceb9a03e77ad86fb7954b17
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Hoist pbmte and hade out of the level loop
These values are constant for every level of pte lookup.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-20-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-20-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 59688aa02340ed51113e5574bf4c3ced3b73220a
https://github.com/qemu/qemu/commit/59688aa02340ed51113e5574bf4c3ced3b73220a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Move leaf pte processing out of level loop
Move the code that never loops outside of the loop.
Unchain the if-return-else statements.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-21-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-21-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0a19bf5e37ded0ebfe48e23defe74cc5d8b162b3
https://github.com/qemu/qemu/commit/0a19bf5e37ded0ebfe48e23defe74cc5d8b162b3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Suppress pte update with is_debug
The debugger should not modify PTE_A or PTE_D.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-22-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-22-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 356c8331d6d922296b4fd5492c22e4178e3fffca
https://github.com/qemu/qemu/commit/356c8331d6d922296b4fd5492c22e4178e3fffca
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Don't modify SUM with is_debug
If we want to give the debugger a greater view of memory than
the cpu, we should simply disable the access check entirely,
not simply for this one corner case.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-23-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-23-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a9d2e3ed4ddbef4f56a007dc6a04509e828cd98f
https://github.com/qemu/qemu/commit/a9d2e3ed4ddbef4f56a007dc6a04509e828cd98f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Merge checks for reserved pte flags
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-24-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-24-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e1dd15076bd8b38ed93cd8fc421f3ba8527af40d
https://github.com/qemu/qemu/commit/e1dd15076bd8b38ed93cd8fc421f3ba8527af40d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Reorg access check in get_physical_address
We were effectively computing the protection bits twice,
once while performing access checks and once while returning
the valid bits to the caller. Reorg so we do this once.
Move the computation of mxr close to its single use.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-25-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-25-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 38303e8a2cfca62e9073014138a5e10f711459ee
https://github.com/qemu/qemu/commit/38303e8a2cfca62e9073014138a5e10f711459ee
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Reorg sum check in get_physical_address
Implement this by adjusting prot, which reduces the set of
checks required. This prevents exec to be set for U pages
in MMUIdx_S_SUM. While it had been technically incorrect,
it did not manifest as a bug, because we will never attempt
to execute from MMUIdx_S_SUM.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-26-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-26-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2e6dba15cd8d3901df6f2e5ebe4db84349100f63
https://github.com/qemu/qemu/commit/2e6dba15cd8d3901df6f2e5ebe4db84349100f63
Author: Ivan Klokov <ivan.klokov@syntacore.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M hw/intc/riscv_aplic.c
Log Message:
-----------
hw/intc/riscv_aplic: Zero init APLIC internal state
Since g_new is used to initialize the RISCVAPLICState->state structure,
in some case we get behavior that is not as expected. This patch
changes this to g_new0, which allows to initialize the APLIC in the correct
state.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-Id: <20230413133432.53771-1-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 85840bd2e032bc412c0cf58c2fb08c1b1f114309
https://github.com/qemu/qemu/commit/85840bd2e032bc412c0cf58c2fb08c1b1f114309
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
A target/riscv/cpu-qom.h
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: add CPU QOM header
QMP CPU commands are usually implemented by a separated file,
<arch>-qmp-cmds.c, to allow them to be build only for softmmu targets.
This file uses a CPU QOM header with basic QOM declarations for the
arch.
We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch,
but first we need a cpu-qom.h header with the definitions of
TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from
cpu.h to the new file, and cpu.h now includes "cpu-qom.h".
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230411183511.189632-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c0177f911f205b3f007df64fbc66fa0ff07caf8e
https://github.com/qemu/qemu/commit/c0177f911f205b3f007df64fbc66fa0ff07caf8e
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M qapi/machine-target.json
M target/riscv/meson.build
A target/riscv/riscv-qmp-cmds.c
Log Message:
-----------
target/riscv: add query-cpy-definitions support
This command is used by tooling like libvirt to retrieve a list of
supported CPUs. Each entry returns a CpuDefinitionInfo object that
contains more information about each CPU.
This initial support includes only the name of the CPU and its typename.
Here's what the command produces for the riscv64 target:
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
{"QMP": {"version": (...)}
{"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
{"return": {}}
{"execute": "query-cpu-definitions"}
{"return": [
{"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated":
false},
{"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false,
"deprecated": false},
{"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":
false},
{"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false,
"deprecated": false},
{"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false,
"deprecated": false},
{"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false,
"deprecated": false},
{"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false,
"deprecated": false}]
}
Next patch will introduce a way to tell whether a given CPU is static or
not.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230411183511.189632-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9e1a30d34212ae05e884c20afad48626cd8070cd
https://github.com/qemu/qemu/commit/9e1a30d34212ae05e884c20afad48626cd8070cd
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/riscv-qmp-cmds.c
Log Message:
-----------
target/riscv: add TYPE_RISCV_DYNAMIC_CPU
This new abstract type will be used to differentiate between static and
non-static CPUs in query-cpu-definitions.
All generic CPUs were changed to be of this type. Named CPUs are kept as
TYPE_RISCV_CPU and will still be considered static.
This is the output of query-cpu-definitions after this change for the
riscv64 target:
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
{"QMP": {"version": (...)}
{"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
{"return": {}}
{"execute": "query-cpu-definitions"}
{"return": [
{"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated":
false},
{"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true,
"deprecated": false},
{"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":
false},
{"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false,
"deprecated": false},
{"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true,
"deprecated": false},
{"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true,
"deprecated": false},
{"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true,
"deprecated": false}
]}
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230411183511.189632-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: eae04c4c131a8d95087c8568eb2cac1988262f25
https://github.com/qemu/qemu/commit/eae04c4c131a8d95087c8568eb2cac1988262f25
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Restore the predicate() NULL check behavior
When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.
This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617.
Some comments are also added to indicate that predicate() must be
provided for an implemented CSR.
Reported-by: Fei Wu <fei2.wu@intel.com>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230417043054.3125614-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7bf14a2f3792a421321ba1087f1b8b16773bf9cd
https://github.com/qemu/qemu/commit/7bf14a2f3792a421321ba1087f1b8b16773bf9cd
Author: Irina Ryapolova <irina.ryapolova@syntacore.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Fix Guest Physical Address Translation
Before changing the flow check for sv39/48/57.
According to specification (for Supervisor mode):
Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB
pages.
Instruction fetch addresses and load and store effective addresses, which are
64 bits,
must have bits 63–39 all equal to bit 38, or else a page-fault exception will
occur.
Likewise for Sv48 and Sv57.
So the high bits are equal to bit 38 for sv39.
According to specification (for Hypervisor mode):
For Sv39x4, address bits of the guest physical address 63:41 must all be zeros,
or else a
guest-page-fault exception occurs.
Likewise for Sv48x4 and Sv57x4.
For Sv48x4 address bits 63:50 must all be zeros, or else a guest-page-fault
exception occurs.
For Sv57x4 address bits 63:59 must all be zeros, or else a guest-page-fault
exception occurs.
For example we are trying to access address 0xffff_ffff_ff01_0000 with only
G-translation enabled.
So expected behavior is to generate exception. But qemu doesn't generate such
exception.
For the old check, we get
va_bits == 41, mask == (1 << 24) - 1, masked_msbs == (0xffff_ffff_ff01_0000 >>
40) & mask == mask.
Accordingly, the condition masked_msbs != 0 && masked_msbs != mask is not
fulfilled
and the check passes.
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230418075423.26217-1-irina.ryapolova@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 190e9f8ec1b79f22097e9bf4aaa93aad7bd7fe69
https://github.com/qemu/qemu/commit/190e9f8ec1b79f22097e9bf4aaa93aad7bd7fe69
Author: Alexandre Ghiti <alexghiti@rivosinc.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
Log Message:
-----------
riscv: Make sure an exception is raised if a pte is malformed
As per the specification, in 64-bit, if any of the pte reserved bits
60-54 is set an exception should be triggered (see 4.4.1, "Addressing and
Memory Protection"). In addition, we must check the napot/pbmt bits are
not set if those extensions are not active.
Reported-by: Andrea Parri <andrea@rivosinc.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230420150220.60919-1-alexghiti@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e1d084a8524a9225a46d485e2d164bb258f326f7
https://github.com/qemu/qemu/commit/e1d084a8524a9225a46d485e2d164bb258f326f7
Author: Rahul Pathak <rpathak@ventanamicro.com>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu_vendorid.h
Log Message:
-----------
target/riscv: add Ventana's Veyron V1 CPU
Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs
exclusively for the rv64 target. It's tested with the 'virt' board.
CPU specs and general information can be found here:
https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230418123624.16414-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a9fe9e191b4305b88c356a1ed9ac3baf89eb18aa
https://github.com/qemu/qemu/commit/a9fe9e191b4305b88c356a1ed9ac3baf89eb18aa
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-05 (Fri, 05 May 2023)
Changed paths:
M MAINTAINERS
M disas/riscv.c
M hw/char/riscv_htif.c
M hw/intc/riscv_aplic.c
M hw/riscv/spike.c
M include/hw/char/riscv_htif.h
M qapi/machine-target.json
M target/riscv/arch_dump.c
A target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/cpu_vendorid.h
M target/riscv/csr.c
M target/riscv/debug.c
M target/riscv/fpu_helper.c
M target/riscv/gdbstub.c
M target/riscv/helper.h
M target/riscv/insn16.decode
M target/riscv/insn_trans/trans_privileged.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvh.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
A target/riscv/insn_trans/trans_rvzce.c.inc
M target/riscv/insn_trans/trans_rvzicond.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/insn_trans/trans_xventanacondops.c.inc
M target/riscv/internals.h
M target/riscv/m128_helper.c
M target/riscv/machine.c
M target/riscv/meson.build
M target/riscv/op_helper.c
M target/riscv/pmp.c
M target/riscv/pmp.h
M target/riscv/pmu.c
A target/riscv/riscv-qmp-cmds.c
M target/riscv/sbi_ecall_interface.h
M target/riscv/time_helper.c
M target/riscv/time_helper.h
M target/riscv/translate.c
M target/riscv/vector_helper.c
A target/riscv/zce_helper.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20230505-1' of
https://github.com/alistair23/qemu into staging
First RISC-V PR for 8.1
* CPURISCVState related cleanup and simplification
* Refactor Zicond and reuse in XVentanaCondOps
* Fix invalid riscv,event-to-mhpmcounters entry
* Support subsets of code size reduction extension
* Fix itrigger when icount is used
* Simplification for RVH related check and code style fix
* Add signature dump function for spike to run ACT tests
* Rework MISA writing
* Fix mstatus.MPP related support
* Use check for relationship between Zdinx/Zhinx{min} and Zfinx
* Fix the H extension TVM trap
* A large collection of mstatus sum changes and cleanups
* Zero init APLIC internal state
* Implement query-cpu-definitions
* Restore the predicate() NULL check behavior
* Fix Guest Physical Address Translation
* Make sure an exception is raised if a pte is malformed
* Add Ventana's Veyron V1 CPU
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# gpg: Signature made Fri 05 May 2023 01:53:35 AM BST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
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* tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu:
(89 commits)
target/riscv: add Ventana's Veyron V1 CPU
riscv: Make sure an exception is raised if a pte is malformed
target/riscv: Fix Guest Physical Address Translation
target/riscv: Restore the predicate() NULL check behavior
target/riscv: add TYPE_RISCV_DYNAMIC_CPU
target/riscv: add query-cpy-definitions support
target/riscv: add CPU QOM header
hw/intc/riscv_aplic: Zero init APLIC internal state
target/riscv: Reorg sum check in get_physical_address
target/riscv: Reorg access check in get_physical_address
target/riscv: Merge checks for reserved pte flags
target/riscv: Don't modify SUM with is_debug
target/riscv: Suppress pte update with is_debug
target/riscv: Move leaf pte processing out of level loop
target/riscv: Hoist pbmte and hade out of the level loop
target/riscv: Hoist second stage mode change to callers
target/riscv: Check SUM in the correct register
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
target/riscv: Move hstatus.spvp check to check_access_hlsv
target/riscv: Introduce mmuidx_2stage
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/f6b761bdbd8b...a9fe9e191b43
- [Qemu-commits] [qemu/qemu] 9c33e0: target/riscv: Avoid env_archcpu() when reading RIS...,
Richard Henderson <=