[Qemu-commits] [qemu/qemu] 487044: target/m68k: Fix gen_load_fp for OS

qemu-commits
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 487044: target/m68k: Fix gen_load_fp for OS_L

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] 487044: target/m68k: Fix gen_load_fp for OS_LONG
Date:	Thu, 11 May 2023 01:06:40 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 4870449e178d047f172c2ae497be01bcf35d0738
      
https://github.com/qemu/qemu/commit/4870449e178d047f172c2ae497be01bcf35d0738
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/m68k/translate.c

  Log Message:
  -----------
  target/m68k: Fix gen_load_fp for OS_LONG

Case was accidentally dropped in b7a94da9550b.

Tested-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: faf852d870e826f6df3bd25ea11d6397fbdfc53c
      
https://github.com/qemu/qemu/commit/faf852d870e826f6df3bd25ea11d6397fbdfc53c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Fix atomic_mmu_lookup for reads

A copy-paste bug had us looking at the victim cache for writes.

Cc: qemu-stable@nongnu.org
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: 08dff435e2 ("tcg: Probe the proper permissions for atomic ops")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20230505204049.352469-1-richard.henderson@linaro.org>


  Commit: 619f02c456ba92720f0b2266911db479ec5be6a9
      
https://github.com/qemu/qemu/commit/619f02c456ba92720f0b2266911db479ec5be6a9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M disas.c

  Log Message:
  -----------
  disas: Fix tabs and braces in disas.c

Fix these before moving the file, for checkpatch.pl.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230510170812.663149-1-richard.henderson@linaro.org>


  Commit: 76ca595b8e43ed037df659b22f802edebc555540
      
https://github.com/qemu/qemu/commit/76ca595b8e43ed037df659b22f802edebc555540
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    R disas.c
    A disas/disas.c
    M disas/meson.build
    M meson.build

  Log Message:
  -----------
  disas: Move disas.c to disas/

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230503072331.1747057-80-richard.henderson@linaro.org>


  Commit: a9d542fed8c3c213e2c1249b0508b694ae92305c
      
https://github.com/qemu/qemu/commit/a9d542fed8c3c213e2c1249b0508b694ae92305c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M bsd-user/elfload.c
    M disas/disas.c
    M include/disas/disas.h
    M linux-user/elfload.c

  Log Message:
  -----------
  disas: Remove target_ulong from the interface

Use uint64_t for the pc, and size_t for the size.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230503072331.1747057-81-richard.henderson@linaro.org>


  Commit: 9275ee3c6fb4e5928fed37071e60169d9d16f436
      
https://github.com/qemu/qemu/commit/9275ee3c6fb4e5928fed37071e60169d9d16f436
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M disas/disas.c
    M include/disas/disas.h

  Log Message:
  -----------
  disas: Remove target-specific headers

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230503072331.1747057-83-richard.henderson@linaro.org>


  Commit: 4e8c91a31c36a3a86615ac6cca602df52738a45a
      
https://github.com/qemu/qemu/commit/4e8c91a31c36a3a86615ac6cca602df52738a45a
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    A disas/disas-internal.h
    A disas/disas-mon.c
    M disas/disas.c
    M disas/meson.build

  Log Message:
  -----------
  disas: Move softmmu specific code to separate file

We'd like to move disas.c into the common code source set, where
CONFIG_USER_ONLY is not available anymore. So we have to move
the related code into a separate file instead.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230508133745.109463-2-thuth@redhat.com>
[rth: Type change done in a separate patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: faef3c061f4c748fd017f2a38415d78f082a8a9a
      
https://github.com/qemu/qemu/commit/faef3c061f4c748fd017f2a38415d78f082a8a9a
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M disas/disas.c
    M disas/meson.build

  Log Message:
  -----------
  disas: Move disas.c into the target-independent source set

By using target_words_bigendian() instead of an ifdef,
we can build this code once.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230508133745.109463-3-thuth@redhat.com>
[rth: Type change done in a separate patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: cea0b9bedcca8b2a34a8ac22a7485e44791ce0b8
      
https://github.com/qemu/qemu/commit/cea0b9bedcca8b2a34a8ac22a7485e44791ce0b8
  Author: Jamie Iles <quic_jiles@quicinc.com>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M cpus-common.c
    M include/exec/cpu-common.h
    M linux-user/elfload.c
    M migration/dirtyrate.c
    M trace/control-target.c

  Log Message:
  -----------
  cpu: expose qemu_cpu_list_lock for lock-guard use

Expose qemu_cpu_list_lock globally so that we can use
WITH_QEMU_LOCK_GUARD and QEMU_LOCK_GUARD to simplify a few code paths
now and in future.

Signed-off-by: Jamie Iles <quic_jiles@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427020925.51003-2-quic_jiles@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e10ee621c22dad076ea02a3a2b3e742c74cc00e9
      
https://github.com/qemu/qemu/commit/e10ee621c22dad076ea02a3a2b3e742c74cc00e9
  Author: Jamie Iles <quic_jiles@quicinc.com>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/tcg-accel-ops-icount.c
    M accel/tcg/tcg-accel-ops-icount.h
    M accel/tcg/tcg-accel-ops-rr.c
    M replay/replay.c

  Log Message:
  -----------
  accel/tcg/tcg-accel-ops-rr: ensure fairness with icount

The round-robin scheduler will iterate over the CPU list with an
assigned budget until the next timer expiry and may exit early because
of a TB exit.  This is fine under normal operation but with icount
enabled and SMP it is possible for a CPU to be starved of run time and
the system live-locks.

For example, booting a riscv64 platform with '-icount
shift=0,align=off,sleep=on -smp 2' we observe a livelock once the kernel
has timers enabled and starts performing TLB shootdowns.  In this case
we have CPU 0 in M-mode with interrupts disabled sending an IPI to CPU
1.  As we enter the TCG loop, we assign the icount budget to next timer
interrupt to CPU 0 and begin executing where the guest is sat in a busy
loop exhausting all of the budget before we try to execute CPU 1 which
is the target of the IPI but CPU 1 is left with no budget with which to
execute and the process repeats.

We try here to add some fairness by splitting the budget across all of
the CPUs on the thread fairly before entering each one.  The CPU count
is cached on CPU list generation ID to avoid iterating the list on each
loop iteration.  With this change it is possible to boot an SMP rv64
guest with icount enabled and no hangs.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <quic_jiles@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427020925.51003-3-quic_jiles@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a964804ff73c94395cee0f35ef3952396a1e473e
      
https://github.com/qemu/qemu/commit/a964804ff73c94395cee0f35ef3952396a1e473e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label,
tcg_out_test_alignment, and some code that lived in both
tcg_out_qemu_ld and tcg_out_qemu_st into one function
that returns HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2227037c2e9814f4be27af93db3eeb6172aa2432
      
https://github.com/qemu/qemu/commit/2227037c2e9814f4be27af93db3eeb6172aa2432
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Use indexed addressing for softmmu fast path

Since tcg_out_{ld,st}_helper_args, the slow path no longer requires
the address argument to be set up by the tlb load sequence.  Use a
plain load for the addend and indexed addressing with the original
input address register.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4bcc26433d893defc0d5d4eec0a5a5e1e3e5fecd
      
https://github.com/qemu/qemu/commit/4bcc26433d893defc0d5d4eec0a5a5e1e3e5fecd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st
into one function that returns HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9bbca0f335f248e90b6e07e94506dd35bc1dd1a1
      
https://github.com/qemu/qemu/commit/9bbca0f335f248e90b6e07e94506dd35bc1dd1a1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, and some code that lived
in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that
returns HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4a61263d46bb81b49a61f0709e037b7bc633db23
      
https://github.com/qemu/qemu/commit/4a61263d46bb81b49a61f0709e037b7bc633db23
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
tcg_out_zext_addr_if_32_bit, and some code that lived in both
tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns
HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e22ded27a81b057f1d8bcc95c565f7251ad0a512
      
https://github.com/qemu/qemu/commit/e22ded27a81b057f1d8bcc95c565f7251ad0a512
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st
into one function that returns HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3d613d944f1d6ec256f805cbd2ead575155d3a21
      
https://github.com/qemu/qemu/commit/3d613d944f1d6ec256f805cbd2ead575155d3a21
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st
into one function that returns HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8809d9f20052d504d29e6ef2e06a4ea8ccc441fa
      
https://github.com/qemu/qemu/commit/8809d9f20052d504d29e6ef2e06a4ea8ccc441fa
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st
into one function that returns TCGReg and TCGLabelQemuLdst.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ee9b3e37f76dd68c6b28b64206622295bdbb5f2f
      
https://github.com/qemu/qemu/commit/ee9b3e37f76dd68c6b28b64206622295bdbb5f2f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
tcg_prepare_user_ldst, and some code that lived in both tcg_out_qemu_ld
and tcg_out_qemu_st into one function that returns HostAddress and
TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f47b432b021dbdd9e6d51569eeab98db5528f3a3
      
https://github.com/qemu/qemu/commit/f47b432b021dbdd9e6d51569eeab98db5528f3a3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add routines for calling slow-path helpers

Add tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.  These and their subroutines
use the existing knowledge of the host function call abi
to load the function call arguments and return results.

These will be used to simplify the backends in turn.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 029e2a7b6e801ed8ad825df6a35da25f5c449379
      
https://github.com/qemu/qemu/commit/029e2a7b6e801ed8ad825df6a35da25f5c449379
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Convert tcg_out_qemu_ld_slow_path

Use tcg_out_ld_helper_args and tcg_out_ld_helper_ret.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 26c9571016a92b172883d948b55e1849c5c7295e
      
https://github.com/qemu/qemu/commit/26c9571016a92b172883d948b55e1849c5c7295e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Convert tcg_out_qemu_st_slow_path

Use tcg_out_st_helper_args.  This eliminates the use of a tail call to
the store helper.  This may or may not be an improvement, depending on
the call/return branch prediction of the host microarchitecture.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8d8388cf976de069fbe1897afd77512f61ce0923
      
https://github.com/qemu/qemu/commit/8d8388cf976de069fbe1897afd77512f61ce0923
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 787e80f85da32c4ce6ad8222c70dab723dba0f41
      
https://github.com/qemu/qemu/commit/787e80f85da32c4ce6ad8222c70dab723dba0f41
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.  This allows our local
tcg_out_arg_* infrastructure to be removed.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9fc1b5fa19444217a59df6c61d527485876af771
      
https://github.com/qemu/qemu/commit/9fc1b5fa19444217a59df6c61d527485876af771
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b72377ddab22cb3e9d8f0611e2938dea73bc6083
      
https://github.com/qemu/qemu/commit/b72377ddab22cb3e9d8f0611e2938dea73bc6083
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.  This allows our local
tcg_out_arg_* infrastructure to be removed.

We are no longer filling the call or return branch
delay slots, nor are we tail-calling for the store,
but this seems a small price to pay.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 351d948a1a185c5ba7bd9e6e12a6d95fb3834139
      
https://github.com/qemu/qemu/commit/351d948a1a185c5ba7bd9e6e12a6d95fb3834139
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a1286d25b20eb60700ed27f792286a58ef9f736e
      
https://github.com/qemu/qemu/commit/a1286d25b20eb60700ed27f792286a58ef9f736e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5972d40ab54d56cadd416380986ef14846bd77f9
      
https://github.com/qemu/qemu/commit/5972d40ab54d56cadd416380986ef14846bd77f9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 79433783d17528930a9a57d9cd3e1550285ae8c4
      
https://github.com/qemu/qemu/commit/79433783d17528930a9a57d9cd3e1550285ae8c4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target-con-set.h
    M tcg/loongarch64/tcg-target-con-str.h
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers.  Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ffbbbc3f9f0d81b7b826bfc1ed1129795217f9bb
      
https://github.com/qemu/qemu/commit/ffbbbc3f9f0d81b7b826bfc1ed1129795217f9bb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h

  Log Message:
  -----------
  tcg/mips: Remove MO_BSWAP handling

While performing the load in the delay slot of the call to the common
bswap helper function is cute, it is not worth the added complexity.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c0e354173aca724edf55b0a5c681fa3efa46b47a
      
https://github.com/qemu/qemu/commit/c0e354173aca724edf55b0a5c681fa3efa46b47a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Reorg tlb load within prepare_host_addr

Compare the address vs the tlb entry with sign-extended values.
This simplifies the page+alignment mask constant, and the
generation of the last byte address for the misaligned test.

Move the tlb addend load up, and the zero-extension down.

This frees up a register, which allows us use TMP3 as the returned base
address register instead of A0, which we were using as a 5th temporary.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e5dbc176f90c23c0feae8838d17728440185dd89
      
https://github.com/qemu/qemu/commit/e5dbc176f90c23c0feae8838d17728440185dd89
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/mips/tcg-target-con-set.h
    M tcg/mips/tcg-target-con-str.h
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-3], not any of the normally available
registers.  Now that we handle overlap betwen inputs and helper arguments,
and have eliminated use of A0, we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 74b7099967c456985d806a8b4547b33f2f69880f
      
https://github.com/qemu/qemu/commit/74b7099967c456985d806a8b4547b33f2f69880f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Reorg tcg_out_tlb_read

Allocate TCG_REG_TMP2.  Use R0, TMP1, TMP2 instead of any of
the normally allocated registers for the tlb load.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: db199c9d79af466f9261227f8aa2f659444dd548
      
https://github.com/qemu/qemu/commit/db199c9d79af466f9261227f8aa2f659444dd548
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target-con-set.h
    M tcg/ppc/tcg-target-con-str.h
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Adjust constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally
available registers.  Now that we handle overlap betwen inputs and
helper arguments, we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9adb9fdc3b2954707e91d886e0687fd48a8e4cde
      
https://github.com/qemu/qemu/commit/9adb9fdc3b2954707e91d886e0687fd48a8e4cde
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target-con-str.h

  Log Message:
  -----------
  tcg/ppc: Remove unused constraints A, B, C, D

These constraints have not been used for quite some time.

Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32")
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ba26d083e83fb716320f714f250013a1bfd935aa
      
https://github.com/qemu/qemu/commit/ba26d083e83fb716320f714f250013a1bfd935aa
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target-con-str.h
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Remove unused constraint J

Never used since its introduction.

Fixes: 3d582c6179c ("tcg-ppc64: Rearrange integer constant constraints")
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d13450677e96f08912fd8549aaab6fc350b645a6
      
https://github.com/qemu/qemu/commit/d13450677e96f08912fd8549aaab6fc350b645a6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target-con-set.h
    M tcg/riscv/tcg-target-con-str.h
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers.  Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: db8ea4ca42ed1fe19de1058f062c5a56289d8df2
      
https://github.com/qemu/qemu/commit/db8ea4ca42ed1fe19de1058f062c5a56289d8df2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Use ALGFR in constructing softmmu host address

Rather than zero-extend the guest address into a register,
use an add instruction which zero-extends the second input.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7dd0eccaab89acfa59eb7108d0bf13f41f54177a
      
https://github.com/qemu/qemu/commit/7dd0eccaab89acfa59eb7108d0bf13f41f54177a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target-con-set.h
    M tcg/s390x/tcg-target-con-str.h
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Simplify constraints on qemu_ld/st

Adjust the softmmu tlb to use R0+R1, not any of the normally available
registers.  Since we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 83be51d69db8f9e8829d8c257e3a3253baca8537
      
https://github.com/qemu/qemu/commit/83be51d69db8f9e8829d8c257e3a3253baca8537
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/mips/tcg/nanomips_translate.c.inc

  Log Message:
  -----------
  target/mips: Add MO_ALIGN to gen_llwp, gen_scwp

These are atomic operations, so mark as requiring alignment.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1a137266785b1cb350b628566df0fbff4f092643
      
https://github.com/qemu/qemu/commit/1a137266785b1cb350b628566df0fbff4f092643
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/mips16e_translate.c.inc
    M target/mips/tcg/mxu_translate.c
    M target/mips/tcg/nanomips_translate.c.inc

  Log Message:
  -----------
  target/mips: Add missing default_tcg_memop_mask

Memory operations that are not already aligned, or otherwise
marked up, require addition of ctx->default_tcg_memop_mask.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b2af65ec1b997aaefd4bd57be9414c3223ecb80f
      
https://github.com/qemu/qemu/commit/b2af65ec1b997aaefd4bd57be9414c3223ecb80f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/mips/tcg/nanomips_translate.c.inc

  Log Message:
  -----------
  target/mips: Use MO_ALIGN instead of 0

The opposite of MO_UNALN is MO_ALIGN.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e422db9b325d41ee520e46efb2d650da4a88b3c1
      
https://github.com/qemu/qemu/commit/e422db9b325d41ee520e46efb2d650da4a88b3c1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M configs/targets/mips-linux-user.mak
    M configs/targets/mips-softmmu.mak
    M configs/targets/mips64-linux-user.mak
    M configs/targets/mips64-softmmu.mak
    M configs/targets/mips64el-linux-user.mak
    M configs/targets/mips64el-softmmu.mak
    M configs/targets/mipsel-linux-user.mak
    M configs/targets/mipsel-softmmu.mak
    M configs/targets/mipsn32-linux-user.mak
    M configs/targets/mipsn32el-linux-user.mak

  Log Message:
  -----------
  target/mips: Remove TARGET_ALIGNED_ONLY

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 17a9023efc31ec1d7f1b4d022d7f34d9a286767b
      
https://github.com/qemu/qemu/commit/17a9023efc31ec1d7f1b4d022d7f34d9a286767b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M configs/targets/nios2-softmmu.mak
    M target/nios2/translate.c

  Log Message:
  -----------
  target/nios2: Remove TARGET_ALIGNED_ONLY

In gen_ldx/gen_stx, the only two locations for memory operations,
mark the operation as either aligned (softmmu) or unaligned
(user-only, as if emulated by the kernel).

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2300417cbc147e232609c0f0ff2de063f11fb47f
      
https://github.com/qemu/qemu/commit/2300417cbc147e232609c0f0ff2de063f11fb47f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/sh4/translate.c

  Log Message:
  -----------
  target/sh4: Use MO_ALIGN where required

Mark all memory operations that are not already marked with UNALIGN.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 63c10ac3cb0a0502de67ec22495f2af1ddf53368
      
https://github.com/qemu/qemu/commit/63c10ac3cb0a0502de67ec22495f2af1ddf53368
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M configs/targets/sh4-linux-user.mak
    M configs/targets/sh4-softmmu.mak
    M configs/targets/sh4eb-linux-user.mak
    M configs/targets/sh4eb-softmmu.mak

  Log Message:
  -----------
  target/sh4: Remove TARGET_ALIGNED_ONLY

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 28602e565557cccf75b6b09f6f73cdd9ac140eda
      
https://github.com/qemu/qemu/commit/28602e565557cccf75b6b09f6f73cdd9ac140eda
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M include/exec/memop.h
    M include/exec/poison.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Remove TARGET_ALIGNED_ONLY

All uses have now been expunged.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e2990491a2702216e8bacb3f2090ee6d6a711be7
      
https://github.com/qemu/qemu/commit/e2990491a2702216e8bacb3f2090ee6d6a711be7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cpu-exec-common.c
    M accel/tcg/internal.h
    M accel/tcg/tb-maint.c

  Log Message:
  -----------
  accel/tcg: Add cpu_in_serial_context

Like cpu_in_exclusive_context, but also true if
there is no other cpu against which we could race.

Use it in tb_flush as a direct replacement.
Use it in cpu_loop_exit_atomic to ensure that there
is no loop against cpu_exec_step_atomic.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 01f11a7323ebf87592e3a5e115e67cb11129b91c
      
https://github.com/qemu/qemu/commit/01f11a7323ebf87592e3a5e115e67cb11129b91c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M include/exec/cpu-defs.h
    M include/exec/cpu_ldst.h

  Log Message:
  -----------
  accel/tcg: Introduce tlb_read_idx

Instead of playing with offsetof in various places, use
MMUAccessType to index an array.  This is easily defined
instead of the previous dummy padding array in the union.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ffa94845e933214dff837c870c19a733cdad590c
      
https://github.com/qemu/qemu/commit/ffa94845e933214dff837c870c19a733cdad590c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Reorg system mode load helpers

Instead of trying to unify all operations on uint64_t, pull out
mmu_lookup() to perform the basic tlb hit and resolution.
Create individual functions to handle access by size.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e6ebc357b42f2a4b81864c5cc02955abf1cf5218
      
https://github.com/qemu/qemu/commit/e6ebc357b42f2a4b81864c5cc02955abf1cf5218
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Reorg system mode store helpers

Instead of trying to unify all operations on uint64_t, use
mmu_lookup() to perform the basic tlb hit and resolution.
Create individual functions to handle access by size.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b2d4d6616c22325dff802e0a35092167f2dc2268
      
https://github.com/qemu/qemu/commit/b2d4d6616c22325dff802e0a35092167f2dc2268
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/loongarch/csr_helper.c
    M target/loongarch/iocsr_helper.c

  Log Message:
  -----------
  target/loongarch: Do not include tcg-ldst.h

This header is supposed to be private to tcg and in fact
does not need to be included here at all.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: db5544e0d363082a3bf3099985520da05d81f1d2
      
https://github.com/qemu/qemu/commit/db5544e0d363082a3bf3099985520da05d81f1d2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cpu-exec-common.c
    M accel/tcg/cputlb.c
    M accel/tcg/internal.h
    M accel/tcg/tb-maint.c
    M accel/tcg/tcg-accel-ops-icount.c
    M accel/tcg/tcg-accel-ops-icount.h
    M accel/tcg/tcg-accel-ops-rr.c
    M bsd-user/elfload.c
    M configs/targets/mips-linux-user.mak
    M configs/targets/mips-softmmu.mak
    M configs/targets/mips64-linux-user.mak
    M configs/targets/mips64-softmmu.mak
    M configs/targets/mips64el-linux-user.mak
    M configs/targets/mips64el-softmmu.mak
    M configs/targets/mipsel-linux-user.mak
    M configs/targets/mipsel-softmmu.mak
    M configs/targets/mipsn32-linux-user.mak
    M configs/targets/mipsn32el-linux-user.mak
    M configs/targets/nios2-softmmu.mak
    M configs/targets/sh4-linux-user.mak
    M configs/targets/sh4-softmmu.mak
    M configs/targets/sh4eb-linux-user.mak
    M configs/targets/sh4eb-softmmu.mak
    M cpus-common.c
    R disas.c
    A disas/disas-internal.h
    A disas/disas-mon.c
    A disas/disas.c
    M disas/meson.build
    M include/disas/disas.h
    M include/exec/cpu-common.h
    M include/exec/cpu-defs.h
    M include/exec/cpu_ldst.h
    M include/exec/memop.h
    M include/exec/poison.h
    M linux-user/elfload.c
    M meson.build
    M migration/dirtyrate.c
    M replay/replay.c
    M target/loongarch/csr_helper.c
    M target/loongarch/iocsr_helper.c
    M target/m68k/translate.c
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/mips16e_translate.c.inc
    M target/mips/tcg/mxu_translate.c
    M target/mips/tcg/nanomips_translate.c.inc
    M target/nios2/translate.c
    M target/sh4/translate.c
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/loongarch64/tcg-target-con-set.h
    M tcg/loongarch64/tcg-target-con-str.h
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/mips/tcg-target-con-set.h
    M tcg/mips/tcg-target-con-str.h
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h
    M tcg/ppc/tcg-target-con-set.h
    M tcg/ppc/tcg-target-con-str.h
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target-con-set.h
    M tcg/riscv/tcg-target-con-str.h
    M tcg/riscv/tcg-target.c.inc
    M tcg/s390x/tcg-target-con-set.h
    M tcg/s390x/tcg-target-con-str.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/tcg.c
    M trace/control-target.c

  Log Message:
  -----------
  Merge tag 'pull-tcg-20230511' of https://gitlab.com/rth7680/qemu into staging

target/m68k: Fix gen_load_fp regression
accel/tcg: Ensure fairness with icount
disas: Move disas.c into the target-independent source sets
tcg: Use common routines for calling slow path helpers
tcg/*: Cleanups to qemu_ld/st constraints
tcg: Remove TARGET_ALIGNED_ONLY
accel/tcg: Reorg system mode load/store helpers

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmRcoWIdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+jNgf+Mp7g/nLUnbSIZ5gU
# 1+Cz26Xv/H+oaUnUl6nyyfhe/MAPsMof71gNp1fh4DXh84sdenCTYiWSAV0RnVyr
# 4eIX08t+5MNm37V4LwPpwl66iiGM7ME7ZpfYK6xBa8t+834IfskCLEGrI2UgUrFx
# G7+FcPwTY0XzRDu6oLtZu/dgVw0FmCWdc6/aEsROJmclVEXXcKeCzXcdcFNoaoDw
# r5tFwJTPXxjycqNYVOoDiXp19T5NWvYFmUaYaOH/OGL+pUbwgCQAk2IGUiPybofs
# 0jqujs94Zb+R1G0kMmS6GPK3jEEGb2wg5fuCkj62rgQJNN+m58MddA6WYjVtdRpt
# yxCU7Q==
# =6wCV
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 11 May 2023 09:03:46 AM BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[ultimate]

* tag 'pull-tcg-20230511' of https://gitlab.com/rth7680/qemu: (53 commits)
  target/loongarch: Do not include tcg-ldst.h
  accel/tcg: Reorg system mode store helpers
  accel/tcg: Reorg system mode load helpers
  accel/tcg: Introduce tlb_read_idx
  accel/tcg: Add cpu_in_serial_context
  tcg: Remove TARGET_ALIGNED_ONLY
  target/sh4: Remove TARGET_ALIGNED_ONLY
  target/sh4: Use MO_ALIGN where required
  target/nios2: Remove TARGET_ALIGNED_ONLY
  target/mips: Remove TARGET_ALIGNED_ONLY
  target/mips: Use MO_ALIGN instead of 0
  target/mips: Add missing default_tcg_memop_mask
  target/mips: Add MO_ALIGN to gen_llwp, gen_scwp
  tcg/s390x: Simplify constraints on qemu_ld/st
  tcg/s390x: Use ALGFR in constructing softmmu host address
  tcg/riscv: Simplify constraints on qemu_ld/st
  tcg/ppc: Remove unused constraint J
  tcg/ppc: Remove unused constraints A, B, C, D
  tcg/ppc: Adjust constraints on qemu_ld/st
  tcg/ppc: Reorg tcg_out_tlb_read
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/fff86d48a2cd...db5544e0d363
[Prev in Thread]
Current Thread
[Next in Thread]
[Qemu-commits] [qemu/qemu] 487044: target/m68k: Fix gen_load_fp for OS_LONG, Richard Henderson <=
Prev by Date: [Qemu-commits] [qemu/qemu] 871cfc: ram: Add public helper to set colo bitmap
Next by Date: [Qemu-commits] [qemu/qemu] a0f06a: target/m68k: Fix gen_load_fp for OS_LONG
Previous by thread: [Qemu-commits] [qemu/qemu] 871cfc: ram: Add public helper to set colo bitmap
Next by thread: [Qemu-commits] [qemu/qemu] a0f06a: target/m68k: Fix gen_load_fp for OS_LONG
Index(es):
- Date
- Thread