[Qemu-commits] [qemu/qemu] d4e4ac: tcg/i386: Set P_REXW in tcg_out_addi

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[Qemu-commits] [qemu/qemu] d4e4ac: tcg/i386: Set P_REXW in tcg_out_addi_

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] d4e4ac: tcg/i386: Set P_REXW in tcg_out_addi_ptr
Date:	Tue, 16 May 2023 12:43:15 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: d4e4ac4a59183fe58017ee38c32e689ac98f3f38
      
https://github.com/qemu/qemu/commit/d4e4ac4a59183fe58017ee38c32e689ac98f3f38
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-14 (Sun, 14 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Set P_REXW in tcg_out_addi_ptr

The REXW bit must be set to produce a 64-bit pointer result; the
bit is disabled in 32-bit mode, so we can do this unconditionally.

Fixes: 7d9e1ee424b0 ("tcg/i386: Adjust assert in tcg_out_addi_ptr")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1592
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1642
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d385d08d87a4bb004c1daf5a61cf457809633a2d
      
https://github.com/qemu/qemu/commit/d385d08d87a4bb004c1daf5a61cf457809633a2d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M include/exec/memop.h
    M tcg/tcg.c

  Log Message:
  -----------
  include/exec/memop: Add MO_ATOM_*

This field may be used to describe the precise atomicity requirements
of the guest, which may then be used to constrain the methods by which
it may be emulated by the host.

For instance, the AArch64 LDP (32-bit) instruction changes semantics
with ARMv8.4 LSE2, from

  MO_64 | MO_ATOM_IFALIGN_PAIR
  (64-bits, single-copy atomic only on 4 byte units,
   nonatomic if not aligned by 4),

to

  MO_64 | MO_ATOM_WITHIN16
  (64-bits, single-copy atomic within a 16 byte block)

The former may be implemented with two 4 byte loads, or a single 8 byte
load if that happens to be efficient on the host.  The latter may not
be implemented with two 4 byte loads and may also require a helper when
misaligned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2a37ccd0b44231070ca36676c45bd4fe1e08cba3
      
https://github.com/qemu/qemu/commit/2a37ccd0b44231070ca36676c45bd4fe1e08cba3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    A accel/tcg/ldst_atomicity.c.inc
    M accel/tcg/user-exec.c

  Log Message:
  -----------
  accel/tcg: Honor atomicity of loads

Create ldst_atomicity.c.inc.

Not required for user-only code loads, because we've ensured that
the page is read-only before beginning to translate code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3564432f466fb7ad475ef085222d6d46a47fb58a
      
https://github.com/qemu/qemu/commit/3564432f466fb7ad475ef085222d6d46a47fb58a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/ldst_atomicity.c.inc
    M accel/tcg/user-exec.c

  Log Message:
  -----------
  accel/tcg: Honor atomicity of stores

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 83577c03e805866f3146d01193d2797409477d39
      
https://github.com/qemu/qemu/commit/83577c03e805866f3146d01193d2797409477d39
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M docs/devel/loads-stores.rst
    M include/tcg/tcg-ldst.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/mips/tcg-target.c.inc
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target.c.inc
    M tcg/s390x/tcg-target.c.inc
    M tcg/sparc64/tcg-target.c.inc
    M tcg/tcg.c
    M tcg/tci.c

  Log Message:
  -----------
  tcg: Unify helper_{be,le}_{ld,st}*

With the current structure of cputlb.c, there is no difference
between the little-endian and big-endian entry points, aside
from the assert.  Unify the pairs of functions.

Hoist the qemu_{ld,st}_helpers arrays to tcg.c.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 42d2f75fcf5ced22a5621a334a92f17ffe61ef2a
      
https://github.com/qemu/qemu/commit/42d2f75fcf5ced22a5621a334a92f17ffe61ef2a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M accel/tcg/user-exec.c
    M include/tcg/tcg-ldst.h
    M tcg/tcg.c

  Log Message:
  -----------
  accel/tcg: Implement helper_{ld,st}*_mmu for user-only

TCG backends may need to defer to a helper to implement
the atomicity required by a given operation.  Mirror the
interface used in system mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 38b8b67dafcaf3708f20c70d43a2c5afb147b6b3
      
https://github.com/qemu/qemu/commit/38b8b67dafcaf3708f20c70d43a2c5afb147b6b3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/tci.c

  Log Message:
  -----------
  tcg/tci: Use helper_{ld,st}*_mmu for user-only

We can now fold these two pieces of code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8df8f9dfc2b0174dfe8a2882c6187534053f9bbd
      
https://github.com/qemu/qemu/commit/8df8f9dfc2b0174dfe8a2882c6187534053f9bbd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/ldst_atomicity.c.inc
    M accel/tcg/tcg-runtime.h
    M accel/tcg/user-exec.c
    M include/tcg/tcg-ldst.h
    M tcg/tcg-op.c

  Log Message:
  -----------
  tcg: Add 128-bit guest memory primitives

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7815e98c0670bd77c1c07405677f6e1668c66e52
      
https://github.com/qemu/qemu/commit/7815e98c0670bd77c1c07405677f6e1668c66e52
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M accel/tcg/ldst_atomicity.c.inc
    M meson.build

  Log Message:
  -----------
  meson: Detect atomic128 support with optimization

There is an edge condition prior to gcc13 for which optimization
is required to generate 16-byte atomic sequences.  Detect this.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b241fd3e111cf80119abb5770e42f29cbe2d888f
      
https://github.com/qemu/qemu/commit/b241fd3e111cf80119abb5770e42f29cbe2d888f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M include/qemu/cpuid.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Add have_atomic16

Notice when Intel or AMD have guaranteed that vmovdqa is atomic.
The new variable will also be used in generated code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5ed9c6a50aaaa4738837f8c24da003c8ce563d5c
      
https://github.com/qemu/qemu/commit/5ed9c6a50aaaa4738837f8c24da003c8ce563d5c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h

  Log Message:
  -----------
  tcg/aarch64: Detect have_lse, have_lse2 for linux

Notice when the host has additional atomic instructions.
The new variables will also be used in generated code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 72be12303ee9c8046426757a6102925c75f0cc7c
      
https://github.com/qemu/qemu/commit/72be12303ee9c8046426757a6102925c75f0cc7c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Detect have_lse, have_lse2 for darwin

These features are present for Apple M1.

Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 552e82a9ec6092dff54b696e20826bdc49c7adaa
      
https://github.com/qemu/qemu/commit/552e82a9ec6092dff54b696e20826bdc49c7adaa
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8223ac3f7df3c3d2b1d0fff9f24acc95ff088f4a
      
https://github.com/qemu/qemu/commit/8223ac3f7df3c3d2b1d0fff9f24acc95ff088f4a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 02b0465f634201fb4aa84dc9b445681bf5613c3a
      
https://github.com/qemu/qemu/commit/02b0465f634201fb4aa84dc9b445681bf5613c3a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c602fa4eb28aa42856ba22da8f65aa8710b58396
      
https://github.com/qemu/qemu/commit/c602fa4eb28aa42856ba22da8f65aa8710b58396
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c562d266b3c0825844f35ce90c37f7cf17ada65a
      
https://github.com/qemu/qemu/commit/c562d266b3c0825844f35ce90c37f7cf17ada65a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8c72c7431d2133a7165fa4ef47345d10b3f160c7
      
https://github.com/qemu/qemu/commit/8c72c7431d2133a7165fa4ef47345d10b3f160c7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/arm/tcg-target-con-set.h
    M tcg/arm/tcg-target-con-str.h
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Adjust constraints on qemu_ld/st

Always reserve r3 for tlb softmmu lookup.  Fix a bug in user-only
ALL_QLDST_REGS, in that r14 is clobbered by the BLNE that leads
to the misaligned trap.  Remove r0+r1 from user-only ALL_QLDST_REGS;
I believe these had been reserved for bswap, which we no longer
perform during qemu_st.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ab85b80f36e539012745da58bdadc50910f7589a
      
https://github.com/qemu/qemu/commit/ab85b80f36e539012745da58bdadc50910f7589a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c7efb55a304232b8d820297a65a6e3fa72edf408
      
https://github.com/qemu/qemu/commit/c7efb55a304232b8d820297a65a6e3fa72edf408
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d493c126c11d0f798768c998498eb11759c26091
      
https://github.com/qemu/qemu/commit/d493c126c11d0f798768c998498eb11759c26091
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 55c376c30e60853d10c429e16e4b253b6ebd5213
      
https://github.com/qemu/qemu/commit/55c376c30e60853d10c429e16e4b253b6ebd5213
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc64: Allocate %g2 as a third temporary

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b3773ccedb9a9333d7b1b89008f69d6011de6959
      
https://github.com/qemu/qemu/commit/b3773ccedb9a9333d7b1b89008f69d6011de6959
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13

Emphasize that the constant is signed.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2ebc650fb6d2bbc8f5596ae612715b72152a2c59
      
https://github.com/qemu/qemu/commit/2ebc650fb6d2bbc8f5596ae612715b72152a2c59
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  target/sparc64: Remove tcg_out_movi_s13 case from tcg_out_movi_imm32

Shuffle the order in tcg_out_movi_int to check s13 first, and
drop this check from tcg_out_movi_imm32.  This might make the
sequence for in_prologue larger, but not worth worrying about.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 907407b257a932a8e36df3adc429d7c745171a06
      
https://github.com/qemu/qemu/commit/907407b257a932a8e36df3adc429d7c745171a06
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32

Emphasize that the constant is unsigned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 868d271fbef1c142e5389294f1ef0f7124ebd1c2
      
https://github.com/qemu/qemu/commit/868d271fbef1c142e5389294f1ef0f7124ebd1c2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-15 (Mon, 15 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc64: Split out tcg_out_movi_s32

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 10dfc1f05fafbf66bf92f768564f80f873a0bf6a
      
https://github.com/qemu/qemu/commit/10dfc1f05fafbf66bf92f768564f80f873a0bf6a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target-con-set.h
    M tcg/sparc64/tcg-target-con-str.h
    M tcg/sparc64/tcg-target.c.inc
    M tcg/sparc64/tcg-target.h

  Log Message:
  -----------
  tcg/sparc64: Use standard slow path for softmmu

Drop the target-specific trampolines for the standard slow path.
This lets us use tcg_out_helper_{ld,st}_args, and handles the new
atomicity bits within MemOp.

At the same time, use the full load/store helpers for user-only mode.
Drop inline unaligned access support for user-only mode, as it does
not handle atomicity.

Use TCG_REG_T[1-3] in the tlb lookup, instead of TCG_REG_O[0-2].
This allows the constraints to be simplified.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 474f48f9a9ecffb7edb5895d5fba172b96974072
      
https://github.com/qemu/qemu/commit/474f48f9a9ecffb7edb5895d5fba172b96974072
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/user-exec.c
    M include/tcg/tcg-ldst.h

  Log Message:
  -----------
  accel/tcg: Remove helper_unaligned_{ld,st}

These functions are now unused.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fba265fe0ff5f8a78c2fe98e160abefc46e97e1b
      
https://github.com/qemu/qemu/commit/fba265fe0ff5f8a78c2fe98e160abefc46e97e1b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Check the host supports unaligned accesses

This should be true of all loongarch64 running Linux.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 54ff67679a5961db3feb4ba3bba1b640695958ca
      
https://github.com/qemu/qemu/commit/54ff67679a5961db3feb4ba3bba1b640695958ca
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Support softmmu unaligned accesses

Test the final byte of an unaligned access.
Use BSTRINS.D to clear the range of bits, rather than AND.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: acde61c3204eeb8dcaa42f43c034871bf196c8f5
      
https://github.com/qemu/qemu/commit/acde61c3204eeb8dcaa42f43c034871bf196c8f5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Support softmmu unaligned accesses

The system is required to emulate unaligned accesses, even if the
hardware does not support it.  The resulting trap may or may not
be more efficient than the qemu slow path.  There are linux kernel
patches in flight to allow userspace to query hardware support;
we can re-evaluate whether to enable this by default after that.

In the meantime, softmmu now matches useronly, where we already
assumed that unaligned accesses are supported.

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c2be4f7947f878e0c81ccda33d47ae4a3667aa2c
      
https://github.com/qemu/qemu/commit/c2be4f7947f878e0c81ccda33d47ae4a3667aa2c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h
    M tcg/arm/tcg-target.c.inc
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.h
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h
    M tcg/riscv/tcg-target.c.inc
    M tcg/riscv/tcg-target.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h
    M tcg/sparc64/tcg-target.c.inc
    M tcg/sparc64/tcg-target.h
    M tcg/tcg-internal.h
    M tcg/tcg-op.c
    M tcg/tci/tcg-target.c.inc
    M tcg/tci/tcg-target.h

  Log Message:
  -----------
  tcg: Introduce tcg_target_has_memory_bswap

Replace the unparameterized TCG_TARGET_HAS_MEMORY_BSWAP macro
with a function with a memop argument.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 57a054390213e442e19c9b06ec9541adacd295af
      
https://github.com/qemu/qemu/commit/57a054390213e442e19c9b06ec9541adacd295af
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M docs/devel/tcg-ops.rst
    M include/tcg/tcg-opc.h
    M tcg/aarch64/tcg-target.h
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target.h
    M tcg/loongarch64/tcg-target.h
    M tcg/mips/tcg-target.h
    M tcg/ppc/tcg-target.h
    M tcg/riscv/tcg-target.h
    M tcg/s390x/tcg-target.h
    M tcg/sparc64/tcg-target.h
    M tcg/tcg-op.c
    M tcg/tcg.c
    M tcg/tci/tcg-target.h

  Log Message:
  -----------
  tcg: Add INDEX_op_qemu_{ld,st}_i128

Add opcodes for backend support for 128-bit memory operations.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3b6afb436a6473b78ee0c69246fe14ba861ccdb2
      
https://github.com/qemu/qemu/commit/3b6afb436a6473b78ee0c69246fe14ba861ccdb2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Introduce tcg_out_movext3

With x86_64 as host, we do not have any temporaries with which to
resolve cycles, but we do have xchg.   As a side bonus, the set of
graphs that can be made with 3 nodes and all nodes conflicting is
small: two.  We can solve the cycle with a single temp.

This is required for x86_64 to handle stores of i128: 1 address
register and 2 data registers.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5ecb2e49d8ac0781b159f0cef2d873121bd24c71
      
https://github.com/qemu/qemu/commit/5ecb2e49d8ac0781b159f0cef2d873121bd24c71
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Merge tcg_out_helper_load_regs into caller

Now that tcg_out_helper_load_regs is not recursive, we can
merge it into its only caller, tcg_out_helper_load_slots.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0a0f084ba186e530160d7f93856121f9fc6ea891
      
https://github.com/qemu/qemu/commit/0a0f084ba186e530160d7f93856121f9fc6ea891
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Support TCG_TYPE_I128 in tcg_out_{ld,st}_helper_{args,ret}

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d13388a325697044e7f7375e1a3f1ad6c81b59b7
      
https://github.com/qemu/qemu/commit/d13388a325697044e7f7375e1a3f1ad6c81b59b7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Introduce atom_and_align_for_opc

Examine MemOp for atomicity and alignment, adjusting alignment
as required to implement atomicity on the host.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8401655a11ce1ce9eba9bb6306f4ea15bd34cf8f
      
https://github.com/qemu/qemu/commit/8401655a11ce1ce9eba9bb6306f4ea15bd34cf8f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Use atom_and_align_for_opc

No change to the ultimate load/store routines yet, so some atomicity
conditions not yet honored, but plumbs the change to alignment through
the relevant functions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 85676de3dc02d4835e1a9e20335b39e01522e360
      
https://github.com/qemu/qemu/commit/85676de3dc02d4835e1a9e20335b39e01522e360
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f681a12d5138606cf4c551dcb2da002d06c620f8
      
https://github.com/qemu/qemu/commit/f681a12d5138606cf4c551dcb2da002d06c620f8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Use atom_and_align_for_opc

No change to the ultimate load/store routines yet, so some atomicity
conditions not yet honored, but plumbs the change to alignment through
the relevant functions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9e52f6db411a6ddb3d54c3fa03336136da21d947
      
https://github.com/qemu/qemu/commit/9e52f6db411a6ddb3d54c3fa03336136da21d947
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2a5129075d389df9cb205b1428b0fb351571393a
      
https://github.com/qemu/qemu/commit/2a5129075d389df9cb205b1428b0fb351571393a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e5433c19ab253fadabd11196c85973169ce62fe3
      
https://github.com/qemu/qemu/commit/e5433c19ab253fadabd11196c85973169ce62fe3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5e0cf10686890ac40d988048fbb81f4c05337570
      
https://github.com/qemu/qemu/commit/5e0cf10686890ac40d988048fbb81f4c05337570
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c519be4fa4968442df46067140f7b8aad014fa3a
      
https://github.com/qemu/qemu/commit/c519be4fa4968442df46067140f7b8aad014fa3a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5db1106902262f70f491dfa6a67542cdfaec463d
      
https://github.com/qemu/qemu/commit/5db1106902262f70f491dfa6a67542cdfaec463d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc64: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8f04e298c248b3b8b80aa5b813a9df24989b1b4e
      
https://github.com/qemu/qemu/commit/8f04e298c248b3b8b80aa5b813a9df24989b1b4e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Honor 64-bit atomicity in 32-bit mode

Use the fpu to perform 64-bit loads and stores.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: caa2e59138458cc0997915740d817bb069fcb8b0
      
https://github.com/qemu/qemu/commit/caa2e59138458cc0997915740d817bb069fcb8b0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Support 128-bit load/store with have_atomic16

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4c5dfb05dc2e9cabc8e75d70617149ac8aeb293a
      
https://github.com/qemu/qemu/commit/4c5dfb05dc2e9cabc8e75d70617149ac8aeb293a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Rename temporaries

We will need to allocate a second general-purpose temporary.
Rename the existing temps to add a distinguishing number.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0e941361bf3b05a1ffb77a47d0321a4f0a6e05f4
      
https://github.com/qemu/qemu/commit/0e941361bf3b05a1ffb77a47d0321a4f0a6e05f4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target-con-set.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h

  Log Message:
  -----------
  tcg/aarch64: Support 128-bit load/store

Use LDXP+STXP when LSE2 is not present and 16-byte atomicity is required,
and LDP/STP otherwise.  This requires allocating a second general-purpose
temporary, as Rs cannot overlap Rn in STXP.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 896471bb176e1a2adfc82d2aba2a5d700ff152c9
      
https://github.com/qemu/qemu/commit/896471bb176e1a2adfc82d2aba2a5d700ff152c9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target-con-set.h
    M tcg/ppc/tcg-target-con-str.h
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h

  Log Message:
  -----------
  tcg/ppc: Support 128-bit load/store

Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required.
Note that these instructions do not require 16-byte alignment.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ddd63a320c28bcf979929cb71a9bdb0770cfc6ab
      
https://github.com/qemu/qemu/commit/ddd63a320c28bcf979929cb71a9bdb0770cfc6ab
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target-con-set.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Support 128-bit load/store

Use LPQ/STPQ when 16-byte atomicity is required.
Note that these instructions require 16-byte alignment.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 308ba8aa42f20ee5128fa4c565e4a2f03c16c3f5
      
https://github.com/qemu/qemu/commit/308ba8aa42f20ee5128fa4c565e4a2f03c16c3f5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/meson.build
    A tcg/tcg-op-ldst.c
    M tcg/tcg-op.c

  Log Message:
  -----------
  tcg: Split out memory ops to tcg-op-ldst.c

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 430f5deaf644edb424399516bc993872e2e181d3
      
https://github.com/qemu/qemu/commit/430f5deaf644edb424399516bc993872e2e181d3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/translate-all.c
    M include/tcg/tcg-op.h
    M include/tcg/tcg-opc.h
    M include/tcg/tcg.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Widen gen_insn_data to uint64_t

We already pass uint64_t to restore_state_to_opc; this changes all
of the other uses from insn_start through the encoding to decoding.

Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9740ece736da789e298e9427345aab0840f623d8
      
https://github.com/qemu/qemu/commit/9740ece736da789e298e9427345aab0840f623d8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c
    M include/tcg/tcg-ldst.h
    M tcg/tcg.c

  Log Message:
  -----------
  accel/tcg: Widen tcg-ldst.h addresses to uint64_t

Always pass the target address as uint64_t.
Adjust tcg_out_{ld,st}_helper_args to match.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f391bdc2603efea2d11a5799e63b5e59b95eda6e
      
https://github.com/qemu/qemu/commit/f391bdc2603efea2d11a5799e63b5e59b95eda6e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/tcg-runtime.h
    M accel/tcg/user-exec.c
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  tcg: Widen helper_{ld,st}_i128 addresses to uint64_t

Always pass the target address as uint64_t.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 26ca714484e8cb828f1b9353ef3a13ab95323c5f
      
https://github.com/qemu/qemu/commit/26ca714484e8cb828f1b9353ef3a13ab95323c5f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/tcg-runtime.h
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  tcg: Widen helper_atomic_* addresses to uint64_t

Always pass the target address as uint64_t.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 17f8242c268723141f8b4e430e65c4173762f8fb
      
https://github.com/qemu/qemu/commit/17f8242c268723141f8b4e430e65c4173762f8fb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/tcg/tcg.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Widen tcg_gen_code pc_start argument to uint64_t

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8b1e132daac91b47f127216ea75fc9e8fc0544e8
      
https://github.com/qemu/qemu/commit/8b1e132daac91b47f127216ea75fc9e8fc0544e8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/plugin-gen.c

  Log Message:
  -----------
  accel/tcg: Merge gen_mem_wrapped with plugin_gen_empty_mem_callback

As gen_mem_wrapped is only used in plugin_gen_empty_mem_callback,
we can avoid the curiosity of union mem_gen_fn by inlining it.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c0e46de672474cef8983220c3dcd6f5da1e28bd6
      
https://github.com/qemu/qemu/commit/c0e46de672474cef8983220c3dcd6f5da1e28bd6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/plugin-gen.c

  Log Message:
  -----------
  accel/tcg: Merge do_gen_mem_cb into caller

As do_gen_mem_cb is called once, merge it into gen_empty_mem_cb.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1935c329de541bf9dc2e8a94b5960f2d08b1466e
      
https://github.com/qemu/qemu/commit/1935c329de541bf9dc2e8a94b5960f2d08b1466e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  tcg: Reduce copies for plugin_gen_mem_callbacks

We only need to make copies for loads, when the destination
overlaps the address.  For now, only eliminate the copy for
stores and 128-bit loads.

Rename plugin_prep_mem_callbacks to plugin_maybe_preserve_addr,
returning NULL if no copy is made.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f0a986749253083d7971797fe04af88bf37be29a
      
https://github.com/qemu/qemu/commit/f0a986749253083d7971797fe04af88bf37be29a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/plugin-gen.c
    M include/exec/plugin-gen.h
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  accel/tcg: Widen plugin_gen_empty_mem_callback to i64

Since we do this inside gen_empty_mem_cb anyway, let's
do this earlier inside tcg expansion.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a7133db2d3f524c2fce64199cdd6b50e7043c0e0
      
https://github.com/qemu/qemu/commit/a7133db2d3f524c2fce64199cdd6b50e7043c0e0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/translate-all.c
    M include/tcg/tcg.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add addr_type to TCGContext

This will enable replacement of TARGET_LONG_BITS within tcg/.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ab524867c4de3a28cbb3ddbe02148ec952242eac
      
https://github.com/qemu/qemu/commit/ab524867c4de3a28cbb3ddbe02148ec952242eac
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/tcg/tcg-op.h
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*

Expand from TCGv to TCGTemp inline in the translators,
and validate that the size matches tcg_ctx->addr_type.
These inlines will eventually be seen only by target-specific code.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fecb1a71ac6a0548fee6c43bbf5d5beacd5d515c
      
https://github.com/qemu/qemu/commit/fecb1a71ac6a0548fee6c43bbf5d5beacd5d515c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/tcg/tcg-op.h
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  tcg: Remove TCGv from tcg_gen_atomic_*

Expand from TCGv to TCGTemp inline in the translators,
and validate that the size matches tcg_ctx->addr_type.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5ecdde4b32264236bb906d6c992d08257f365697
      
https://github.com/qemu/qemu/commit/5ecdde4b32264236bb906d6c992d08257f365697
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/tcg/tcg-opc.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/mips/tcg-target.c.inc
    M tcg/optimize.c
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target.c.inc
    M tcg/s390x/tcg-target.c.inc
    M tcg/sparc64/tcg-target.c.inc
    M tcg/tcg-op-ldst.c
    M tcg/tcg.c
    M tcg/tci.c
    M tcg/tci/tcg-target.c.inc

  Log Message:
  -----------
  tcg: Split INDEX_op_qemu_{ld,st}* for guest address size

For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits,
as we need one or two host registers to represent the guest address.

Create the new opcodes and update all users.  Since we have not
yet eliminated TARGET_LONG_BITS, only one of the two opcodes will
ever be used, so we can get away with treating them the same in
the backends.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 759fbfb3aeed75c88c686f4f6e8936175aeceda2
      
https://github.com/qemu/qemu/commit/759fbfb3aeed75c88c686f4f6e8936175aeceda2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tci.c
    M tcg/tci/tcg-target.c.inc

  Log Message:
  -----------
  tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong

We now have the address size as part of the opcode, so
we no longer need to test TARGET_LONG_BITS.  We can use
uint64_t for target_ulong, as passed into load/store helpers.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fb9d7df8b73caee6a42e7d7706d34f57542ae35d
      
https://github.com/qemu/qemu/commit/fb9d7df8b73caee6a42e7d7706d34f57542ae35d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32

Keep all 32-bit values zero extended in the register, not solely when
addresses are 32 bits.  This eliminates a dependency on TARGET_LONG_BITS.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: df6d59421aa747ec7aca574d835102b9a3ec18bf
      
https://github.com/qemu/qemu/commit/df6d59421aa747ec7aca574d835102b9a3ec18bf
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Conditionalize tcg_out_extu_i32_i64

Since TCG_TYPE_I32 values are kept zero-extended in registers, via
omission of the REXW bit, we need not extend if the register matches.
This is already relied upon by qemu_{ld,st}.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c7a1d674a7497444ffdefa40f038098e08dc3b74
      
https://github.com/qemu/qemu/commit/c7a1d674a7497444ffdefa40f038098e08dc3b74
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Adjust type of tlb_mask

Because of its use on tgen_arithi, this value must be a signed
32-bit quantity, as that is what may be encoded in the insn.
The truncation of the value to unsigned for 32-bit guests is
done via the REX bit via 'trexw'.

Removes the only uses of target_ulong from this tcg backend.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c5b29069a8f41fdfd2704db8ed57dd32b1afa731
      
https://github.com/qemu/qemu/commit/c5b29069a8f41fdfd2704db8ed57dd32b1afa731
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL

All uses can be infered from the INDEX_op_qemu_*_a{32,64}_* opcode
being used.  Add a field into TCGLabelQemuLdst to record the usage.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8042c2f719ee2d60a20604f741480ab15564dc7d
      
https://github.com/qemu/qemu/commit/8042c2f719ee2d60a20604f741480ab15564dc7d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Remove TARGET_LONG_BITS

All uses can be infered from the INDEX_op_qemu_*_a{32,64}_*
opcode being used.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4a3c71bff9ccd1d64b61d861afdabb2e1d566582
      
https://github.com/qemu/qemu/commit/4a3c71bff9ccd1d64b61d861afdabb2e1d566582
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Remove USE_GUEST_BASE

Eliminate the test vs TARGET_LONG_BITS by considering this
predicate to be always true, and simplify accordingly.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: bb52a8e8a9f0ebf3b46aa2280354226277492fb4
      
https://github.com/qemu/qemu/commit/bb52a8e8a9f0ebf3b46aa2280354226277492fb4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL

All uses replaced with TCGContext.addr_type.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a037ce86745ab57de6e9c1af4fc4f70f24ff3fa5
      
https://github.com/qemu/qemu/commit/a037ce86745ab57de6e9c1af4fc4f70f24ff3fa5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL

All uses replaced with TCGContext.addr_type.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f214d88c73cf5766de5b3c06554d377befd4f7c5
      
https://github.com/qemu/qemu/commit/f214d88c73cf5766de5b3c06554d377befd4f7c5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL

All uses replaced with TCGContext.addr_type.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2856edf3131bb154a8af3c4c74ac34c4e0e195f1
      
https://github.com/qemu/qemu/commit/2856edf3131bb154a8af3c4c74ac34c4e0e195f1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL

All uses replaced with TCGContext.addr_type.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9573fcd7bb6ec68220202beeb03c658ad0f183fa
      
https://github.com/qemu/qemu/commit/9573fcd7bb6ec68220202beeb03c658ad0f183fa
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/translate-all.c
    M include/tcg/tcg.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/mips/tcg-target.c.inc
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target.c.inc
    M tcg/s390x/tcg-target.c.inc
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg: Add page_bits and page_mask to TCGContext

Disconnect guest page size from TCG compilation.
While this could be done via exec/target_page.h, we want to cache
the value across multiple memory access operations, so we might
as well initialize this early.

The changes within tcg/ are entirely mechanical:

    sed -i s/TARGET_PAGE_BITS/s->page_bits/g
    sed -i s/TARGET_PAGE_MASK/s->page_mask/g

Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9e61a77d8198e7579639e58c91306a0c14e756d7
      
https://github.com/qemu/qemu/commit/9e61a77d8198e7579639e58c91306a0c14e756d7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/translate-all.c
    M include/tcg/tcg.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg: Add tlb_dyn_max_bits to TCGContext

Disconnect guest tlb parameters from TCG compilation.

Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ee95d036bf4bfa10be65325a287bf3d0e8b2a0e6
      
https://github.com/qemu/qemu/commit/ee95d036bf4bfa10be65325a287bf3d0e8b2a0e6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/exec/cpu-all.h
    A include/exec/user/guest-base.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Split out exec/user/guest-base.h

TCG will need this declaration, without all of the other
bits that come with cpu-all.h.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ee58e412fde9ad7015230754e66cec2bc324aab0
      
https://github.com/qemu/qemu/commit/ee58e412fde9ad7015230754e66cec2bc324aab0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/cputlb.c
    A accel/tcg/ldst_atomicity.c.inc
    M accel/tcg/plugin-gen.c
    M accel/tcg/tcg-runtime.h
    M accel/tcg/translate-all.c
    M accel/tcg/user-exec.c
    M docs/devel/loads-stores.rst
    M docs/devel/tcg-ops.rst
    M include/exec/cpu-all.h
    M include/exec/memop.h
    M include/exec/plugin-gen.h
    A include/exec/user/guest-base.h
    M include/qemu/cpuid.h
    M include/tcg/tcg-ldst.h
    M include/tcg/tcg-op.h
    M include/tcg/tcg-opc.h
    M include/tcg/tcg.h
    M meson.build
    M tcg/aarch64/tcg-target-con-set.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h
    M tcg/arm/tcg-target-con-set.h
    M tcg/arm/tcg-target-con-str.h
    M tcg/arm/tcg-target.c.inc
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.h
    M tcg/meson.build
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h
    M tcg/optimize.c
    M tcg/ppc/tcg-target-con-set.h
    M tcg/ppc/tcg-target-con-str.h
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h
    M tcg/riscv/tcg-target.c.inc
    M tcg/riscv/tcg-target.h
    M tcg/s390x/tcg-target-con-set.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h
    M tcg/sparc64/tcg-target-con-set.h
    M tcg/sparc64/tcg-target-con-str.h
    M tcg/sparc64/tcg-target.c.inc
    M tcg/sparc64/tcg-target.h
    M tcg/tcg-internal.h
    A tcg/tcg-op-ldst.c
    M tcg/tcg-op.c
    M tcg/tcg.c
    M tcg/tci.c
    M tcg/tci/tcg-target.c.inc
    M tcg/tci/tcg-target.h

  Log Message:
  -----------
  Merge tag 'pull-tcg-20230516' of https://gitlab.com/rth7680/qemu into staging

tcg/i386: Fix tcg_out_addi_ptr for win64
tcg: Implement atomicity for TCGv_i128
tcg: First quarter of cleanups for building tcg once

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmRj3DcdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9ZNQf/aajyN/mId/kL+HtW
# kX1bClBv47wJIfXFdj7HGUkxiB7fkfwFuu0AzwBzY3Hcc5SQWdemH6SlmlR9h8N1
# /bhXYR122pIaJFx6crzJiwb8/WjyvcEYQcx29ATaw70Rfmls5abGC6IcA2lc/g/u
# 7f1zrXKio7xWJi/Lhp8qQlxRBdGUBQFdJ4oK6pFW/ksInB3O1Bkb3s6f6vmuklGY
# +kzegOv19qaRSSCDR6Liq95OtJdYTl32LpDW7yi7efeKXLAnyy4YqI3BTUfrunfW
# iQKqRqsE9CMBak4m6QO7R/FAdPMxTdE6Cw7ScQmmSxe2GhrET5kL8R9oYgzEJIeu
# kdOjjw==
# =I6o3
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 16 May 2023 12:40:39 PM PDT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[ultimate]

* tag 'pull-tcg-20230516' of https://gitlab.com/rth7680/qemu: (80 commits)
  tcg: Split out exec/user/guest-base.h
  tcg: Add tlb_dyn_max_bits to TCGContext
  tcg: Add page_bits and page_mask to TCGContext
  tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL
  tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL
  tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
  tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
  tcg/aarch64: Remove USE_GUEST_BASE
  tcg/arm: Remove TARGET_LONG_BITS
  tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL
  tcg/i386: Adjust type of tlb_mask
  tcg/i386: Conditionalize tcg_out_extu_i32_i64
  tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32
  tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
  tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
  tcg: Remove TCGv from tcg_gen_atomic_*
  tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*
  tcg: Add addr_type to TCGContext
  accel/tcg: Widen plugin_gen_empty_mem_callback to i64
  tcg: Reduce copies for plugin_gen_mem_callbacks
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/f9d58e0ca53b...ee58e412fde9
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