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[Qemu-commits] [qemu/qemu] d5920b: tcg: Remove TCGv from tcg_gen_qemu_{l
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] d5920b: tcg: Remove TCGv from tcg_gen_qemu_{ld, st}_* |
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Date: |
Tue, 16 May 2023 21:31:00 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: d5920b7280762d4d696bff87f50dbce453adef06
https://github.com/qemu/qemu/commit/d5920b7280762d4d696bff87f50dbce453adef06
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M include/tcg/tcg-op.h
M tcg/tcg-op-ldst.c
Log Message:
-----------
tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*
Expand from TCGv to TCGTemp inline in the translators,
and validate that the size matches tcg_ctx->addr_type.
These inlines will eventually be seen only by target-specific code.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0700ceb3939f08619d7f323209597ef62b489514
https://github.com/qemu/qemu/commit/0700ceb3939f08619d7f323209597ef62b489514
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M include/tcg/tcg-op.h
M tcg/tcg-op-ldst.c
Log Message:
-----------
tcg: Remove TCGv from tcg_gen_atomic_*
Expand from TCGv to TCGTemp inline in the translators,
and validate that the size matches tcg_ctx->addr_type.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fecccfcc542370caedbfc09fe9963d128f5e73a0
https://github.com/qemu/qemu/commit/fecccfcc542370caedbfc09fe9963d128f5e73a0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M include/tcg/tcg-opc.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits,
as we need one or two host registers to represent the guest address.
Create the new opcodes and update all users. Since we have not
yet eliminated TARGET_LONG_BITS, only one of the two opcodes will
ever be used, so we can get away with treating them the same in
the backends.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: dd7dc93ef056509edd1ec47f7a1d8a7bde9c411f
https://github.com/qemu/qemu/commit/dd7dc93ef056509edd1ec47f7a1d8a7bde9c411f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
We now have the address size as part of the opcode, so
we no longer need to test TARGET_LONG_BITS. We can use
uint64_t for target_ulong, as passed into load/store helpers.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7a9ccb869c31430ac8a852ae45ea95023b2d0d34
https://github.com/qemu/qemu/commit/7a9ccb869c31430ac8a852ae45ea95023b2d0d34
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/i386/tcg-target.h
Log Message:
-----------
tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32
Keep all 32-bit values zero extended in the register, not solely when
addresses are 32 bits. This eliminates a dependency on TARGET_LONG_BITS.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b2485530d8873f8c3a4f32bf718a52527e7d2981
https://github.com/qemu/qemu/commit/b2485530d8873f8c3a4f32bf718a52527e7d2981
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Conditionalize tcg_out_extu_i32_i64
Since TCG_TYPE_I32 values are kept zero-extended in registers, via
omission of the REXW bit, we need not extend if the register matches.
This is already relied upon by qemu_{ld,st}.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c60ad6e3b9be0c9622811715ffdd921bfd6ea7d2
https://github.com/qemu/qemu/commit/c60ad6e3b9be0c9622811715ffdd921bfd6ea7d2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Adjust type of tlb_mask
Because of its use on tgen_arithi, this value must be a signed
32-bit quantity, as that is what may be encoded in the insn.
The truncation of the value to unsigned for 32-bit guests is
done via the REX bit via 'trexw'.
Removes the only uses of target_ulong from this tcg backend.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 63f4da91f955f6ca1d1d3264a2e0d9fdd22bc33e
https://github.com/qemu/qemu/commit/63f4da91f955f6ca1d1d3264a2e0d9fdd22bc33e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL
All uses can be infered from the INDEX_op_qemu_*_a{32,64}_* opcode
being used. Add a field into TCGLabelQemuLdst to record the usage.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 03a2ecdab17e8410483e7c41af7386ccfce4dd6e
https://github.com/qemu/qemu/commit/03a2ecdab17e8410483e7c41af7386ccfce4dd6e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Remove TARGET_LONG_BITS
All uses can be infered from the INDEX_op_qemu_*_a{32,64}_*
opcode being used.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 52533157568c1b8df04821759bdcf24b29a25b83
https://github.com/qemu/qemu/commit/52533157568c1b8df04821759bdcf24b29a25b83
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Remove USE_GUEST_BASE
Eliminate the test vs TARGET_LONG_BITS by considering this
predicate to be always true, and simplify accordingly.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 60c452a1a2aaf100830256e02dc09ff7a85ad6a7
https://github.com/qemu/qemu/commit/60c452a1a2aaf100830256e02dc09ff7a85ad6a7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
All uses replaced with TCGContext.addr_type.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6e2a21b70b9308292b8bc0e67c2b0b42f0cdb5b8
https://github.com/qemu/qemu/commit/6e2a21b70b9308292b8bc0e67c2b0b42f0cdb5b8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
All uses replaced with TCGContext.addr_type.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5e983cbc2e18b471c26f68dad83853330393da35
https://github.com/qemu/qemu/commit/5e983cbc2e18b471c26f68dad83853330393da35
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL
All uses replaced with TCGContext.addr_type.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c31e5fa44d0ebd2e78f1ead2147e30cd137ae5e7
https://github.com/qemu/qemu/commit/c31e5fa44d0ebd2e78f1ead2147e30cd137ae5e7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL
All uses replaced with TCGContext.addr_type.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: aece72b76bfeffcab715cd62742fd7f366ceb079
https://github.com/qemu/qemu/commit/aece72b76bfeffcab715cd62742fd7f366ceb079
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M accel/tcg/translate-all.c
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
Log Message:
-----------
tcg: Add page_bits and page_mask to TCGContext
Disconnect guest page size from TCG compilation.
While this could be done via exec/target_page.h, we want to cache
the value across multiple memory access operations, so we might
as well initialize this early.
The changes within tcg/ are entirely mechanical:
sed -i s/TARGET_PAGE_BITS/s->page_bits/g
sed -i s/TARGET_PAGE_MASK/s->page_mask/g
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a66efde188e43041277822e582de1c897b966792
https://github.com/qemu/qemu/commit/a66efde188e43041277822e582de1c897b966792
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M accel/tcg/translate-all.c
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg: Add tlb_dyn_max_bits to TCGContext
Disconnect guest tlb parameters from TCG compilation.
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7d478306e84259678b2941e8af7496ef32a9c4c5
https://github.com/qemu/qemu/commit/7d478306e84259678b2941e8af7496ef32a9c4c5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M include/exec/cpu-all.h
A include/exec/user/guest-base.h
M tcg/tcg.c
Log Message:
-----------
tcg: Split out exec/user/guest-base.h
TCG will need this declaration, without all of the other
bits that come with cpu-all.h.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6972ef1440a9d685482d78672620a7482f2bd09a
https://github.com/qemu/qemu/commit/6972ef1440a9d685482d78672620a7482f2bd09a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-16 (Tue, 16 May 2023)
Changed paths:
M accel/tcg/atomic_common.c.inc
M accel/tcg/cputlb.c
A accel/tcg/ldst_atomicity.c.inc
M accel/tcg/plugin-gen.c
M accel/tcg/tcg-runtime.h
M accel/tcg/translate-all.c
M accel/tcg/user-exec.c
M docs/devel/loads-stores.rst
M docs/devel/tcg-ops.rst
M include/exec/cpu-all.h
M include/exec/memop.h
M include/exec/plugin-gen.h
A include/exec/user/guest-base.h
M include/qemu/cpuid.h
M include/tcg/tcg-ldst.h
M include/tcg/tcg-op.h
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M meson.build
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target-con-str.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
M tcg/meson.build
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target-con-str.h
M tcg/sparc64/tcg-target.c.inc
M tcg/sparc64/tcg-target.h
M tcg/tcg-internal.h
A tcg/tcg-op-ldst.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
Log Message:
-----------
Merge tag 'pull-tcg-20230516-3' of https://gitlab.com/rth7680/qemu into
staging
tcg/i386: Fix tcg_out_addi_ptr for win64
tcg: Implement atomicity for TCGv_i128
tcg: First quarter of cleanups for building tcg once
# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmRkWC8dHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/I+wf8CUF+J/E9u0EuurrB
# 1asDicANUJIACnqlcEpSPKuSMtbzo1RDTQUR+d3GWJjyLASvSJZFZTQqWBdACRpc
# sNuDz3/1a6FbiM14CwIVmPpcjQXa+18Ck670Chmw51KyEt2xyDJTySFIGEqjiuTf
# YVDBbOs8neFZdcDvAs1qNUTjhRj4nNtkpQoBpv0tGH7E0CzPp6OcvxwfieVyLOIa
# Cy1ELM3aMyVN5MTjnORYLK70Pa9emdjB88SlypZx363ARKC7B50lzYPQ4E5zrOZq
# FKrOq5nFWLCtn4BID0R+jUmuUP6znR/hTlToDmf/9B4j9TUivERWlc54lz3YU6Gn
# su3FKg==
# =LVOb
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 16 May 2023 09:29:35 PM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[ultimate]
* tag 'pull-tcg-20230516-3' of https://gitlab.com/rth7680/qemu: (74 commits)
tcg: Split out exec/user/guest-base.h
tcg: Add tlb_dyn_max_bits to TCGContext
tcg: Add page_bits and page_mask to TCGContext
tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/aarch64: Remove USE_GUEST_BASE
tcg/arm: Remove TARGET_LONG_BITS
tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/i386: Adjust type of tlb_mask
tcg/i386: Conditionalize tcg_out_extu_i32_i64
tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32
tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
tcg: Remove TCGv from tcg_gen_atomic_*
tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*
tcg: Add addr_type to TCGContext
accel/tcg: Widen plugin_gen_empty_mem_callback to i64
tcg: Reduce copies for plugin_gen_mem_callbacks
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/1c3a828a4ede...6972ef1440a9
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