[Qemu-commits] [qemu/qemu] 187727: sbsa-ref: switch default cpu core to Neoverse-N1

[Richard Henderson]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 1877272bad7b08b67312503ee66184279876c7bd
      
https://github.com/qemu/qemu/commit/1877272bad7b08b67312503ee66184279876c7bd
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  sbsa-ref: switch default cpu core to Neoverse-N1

The world outside moves to newer and newer cpu cores. Let move SBSA
Reference Platform to something newer as well.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20230506183417.1360427-1-marcin.juszkiewicz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a6771f2f5cbfbf312e2fb5b1627f38a6bf6321d0
      
https://github.com/qemu/qemu/commit/a6771f2f5cbfbf312e2fb5b1627f38a6bf6321d0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/sve_helper.c

  Log Message:
  -----------
  target/arm: Fix vd == vm overlap in sve_ldff1_z

If vd == vm, copy vm to scratch, so that we can pre-zero
the output and still access the gather indicies.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1612
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230504104232.1877774-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 96e6d25fdd5f6cd0f9b8eef6c8ab1365509c4aa2
      
https://github.com/qemu/qemu/commit/96e6d25fdd5f6cd0f9b8eef6c8ab1365509c4aa2
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  Maintainers: add myself as reviewer for sbsa-ref

At Linaro I work on sbsa-ref, know direction it goes.

May not get code details each time.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230515143753.365591-1-marcin.juszkiewicz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b320e21c48ce64853904bea6631c0158cc2ef227
      
https://github.com/qemu/qemu/commit/b320e21c48ce64853904bea6631c0158cc2ef227
  Author: Cornelia Huck <cohuck@redhat.com>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M hw/arm/virt.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/kvm.c
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  arm/kvm: add support for MTE

Extend the 'mte' property for the virt machine to cover KVM as
well. For KVM, we don't allocate tag memory, but instead enable the
capability.

If MTE has been enabled, we need to disable migration, as we do not
yet have a way to migrate the tags as well. Therefore, MTE will stay
off with KVM unless requested explicitly.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230428095533.21747-2-cohuck@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 70a670cadba8e3669af138fbb8c0ef377c5b09ff
      
https://github.com/qemu/qemu/commit/70a670cadba8e3669af138fbb8c0ef377c5b09ff
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/debug_helper.c

  Log Message:
  -----------
  target/arm: add RAZ/WI handling for DBGDTR[TX|RX]

The commit b3aa2f2128 (target/arm: provide stubs for more external
debug registers) was added to handle HyperV's unconditional usage of
Debug Communications Channel. It turns out that Linux will similarly
break if you enable CONFIG_HVC_DCC "ARM JTAG DCC console".

Extend the registers we RAZ/WI set to avoid this.

Cc: Anders Roxell <anders.roxell@linaro.org>
Cc: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230516104420.407912-1-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9162ac6b9ee5f9d91d8e76386b3ef389fd360a0c
      
https://github.com/qemu/qemu/commit/9162ac6b9ee5f9d91d8e76386b3ef389fd360a0c
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  sbsa-ref: use Bochs graphics card instead of VGA

Bochs card is normal PCI Express card so it fits better in system with
PCI Express bus. VGA is simple legacy PCI card.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20230505120936.1097060-1-marcin.juszkiewicz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8ed24ba17abc2a6f072f9631a05d871d9eb7fc7e
      
https://github.com/qemu/qemu/commit/8ed24ba17abc2a6f072f9631a05d871d9eb7fc7e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Split out disas_a64_legacy

Split out all of the decode stuff from aarch64_tr_translate_insn.
Call it disas_a64_legacy to indicate it will be replaced.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-2-peter.maydell@linaro.org
[PMM: Rebased]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8058c8316f1081ea6ddedef4db647d327e2e2488
      
https://github.com/qemu/qemu/commit/8058c8316f1081ea6ddedef4db647d327e2e2488
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    A target/arm/tcg/a64.decode
    M target/arm/tcg/meson.build
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Create decodetree skeleton for A64

The A64 translator uses a hand-written decoder for everything except
SVE or SME.  It's fairly well structured, but it's becoming obvious
that it's still more painful to add instructions to than the A32
translator, because putting a new instruction into the right place in
a hand-written decoder is much harder than adding new instruction
patterns to a decodetree file.

As the first step in conversion to decodetree, create the skeleton of
the decodetree decoder; where it does not handle instructions we will
fall back to the legacy decoder (which will be for everything at the
moment, since there are no patterns in a64.decode).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-3-peter.maydell@linaro.org


  Commit: 270076d01ac6bc7cd2a6e0830507c5f5f538d161
      
https://github.com/qemu/qemu/commit/270076d01ac6bc7cd2a6e0830507c5f5f538d161
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Pull calls to disas_sve() and disas_sme() out of legacy decoder

The SVE and SME decode is already done by decodetree.  Pull the calls
to these decoders out of the legacy decoder.  This doesn't change
behaviour because all the patterns in sve.decode and sme.decode
already require the bits that the legacy decoder is decoding to have
the correct values.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-4-peter.maydell@linaro.org


  Commit: 45fda88ea2185699c2bc1e3339a16db59b40eb72
      
https://github.com/qemu/qemu/commit/45fda88ea2185699c2bc1e3339a16db59b40eb72
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert PC-rel addressing to decodetree

Convert the ADR and ADRP instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-5-peter.maydell@linaro.org
[PMM: Rebased]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 372b7ec3a88fb9a273d71b63a9c3e340a66c2a1b
      
https://github.com/qemu/qemu/commit/372b7ec3a88fb9a273d71b63a9c3e340a66c2a1b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Split gen_add_CC and gen_sub_CC

Split out specific 32-bit and 64-bit functions.
These carry the same signature as tcg_gen_add_i64,
and so will be easier to pass as callbacks.

Retain gen_add_CC and gen_sub_CC during conversion.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-6-peter.maydell@linaro.org
[PMM: rebased]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3ce7b5ea73bf0fb0f04b30af671d5aa6db3039de
      
https://github.com/qemu/qemu/commit/3ce7b5ea73bf0fb0f04b30af671d5aa6db3039de
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Convert Add/subtract (immediate) to decodetree

Convert the ADD and SUB (immediate) instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-7-peter.maydell@linaro.org
[PMM: Rebased; adjusted to use translate.h's TRANS macro]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 86002eccb947b76870daf19178a455f1b2e13b03
      
https://github.com/qemu/qemu/commit/86002eccb947b76870daf19178a455f1b2e13b03
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert Add/subtract (immediate with tags) to decodetree

Convert the ADDG and SUBG (immediate) instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-8-peter.maydell@linaro.org
[PMM: Rebased; use TRANS_FEAT()]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 000bcd008f45c630710c81c5df0b1a5ef0d5a8bb
      
https://github.com/qemu/qemu/commit/000bcd008f45c630710c81c5df0b1a5ef0d5a8bb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Replace bitmask64 with MAKE_64BIT_MASK

Use the bitops.h macro rather than rolling our own here.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-9-peter.maydell@linaro.org


  Commit: 8127f46a5b6b55b9a8bd85be21f99708e3150d9f
      
https://github.com/qemu/qemu/commit/8127f46a5b6b55b9a8bd85be21f99708e3150d9f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert Logical (immediate) to decodetree

Convert the ADD, ORR, EOR, ANDS (immediate) instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-10-peter.maydell@linaro.org
[PMM: rebased]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ee0daeb94627231365cb7748dc8eda1c73abb79b
      
https://github.com/qemu/qemu/commit/ee0daeb94627231365cb7748dc8eda1c73abb79b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert Move wide (immediate) to decodetree

Convert the MON, MOVZ, MOVK instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-11-peter.maydell@linaro.org
[PMM: Rebased]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5e451ae63ba05bafb01516bdf82830cb2f102201
      
https://github.com/qemu/qemu/commit/5e451ae63ba05bafb01516bdf82830cb2f102201
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert Bitfield to decodetree

Convert the BFM, SBFM, UBFM instructions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230512144106.3608981-12-peter.maydell@linaro.org
[PMM: Rebased]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4240fb6175ea824f5c65cd346bd4086dd92353c2
      
https://github.com/qemu/qemu/commit/4240fb6175ea824f5c65cd346bd4086dd92353c2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert Extract instructions to decodetree

Convert the EXTR instruction to decodetree (this is the
only one in the 'Extract" class). This is the last of
the dp-immediate insns in the legacy decoder, so we
can now remove disas_data_proc_imm().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-13-peter.maydell@linaro.org


  Commit: 6201b2a4d050548731eae88c770106352271749e
      
https://github.com/qemu/qemu/commit/6201b2a4d050548731eae88c770106352271749e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert unconditional branch immediate to decodetree

Convert the unconditional branch immediate insns B and BL to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-14-peter.maydell@linaro.org


  Commit: f8977d50fc43176ca33796e36e7cd40e809c3628
      
https://github.com/qemu/qemu/commit/f8977d50fc43176ca33796e36e7cd40e809c3628
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert CBZ, CBNZ to decodetree

Convert the compare-and-branch-immediate insns CBZ and CBNZ
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-15-peter.maydell@linaro.org


  Commit: e505828d3088abe306243e713d57b0563246c6b1
      
https://github.com/qemu/qemu/commit/e505828d3088abe306243e713d57b0563246c6b1
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert TBZ, TBNZ to decodetree

Convert the test-and-branch-immediate insns TBZ and TBNZ
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-16-peter.maydell@linaro.org


  Commit: 484df362dd5e57ca2043f759257d477194fa3703
      
https://github.com/qemu/qemu/commit/484df362dd5e57ca2043f759257d477194fa3703
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert conditional branch insns to decodetree

Convert the immediate conditional branch insn B.cond to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-17-peter.maydell@linaro.org


  Commit: c0b5e3943b14298010384eb817b58458a97c5b22
      
https://github.com/qemu/qemu/commit/c0b5e3943b14298010384eb817b58458a97c5b22
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert BR, BLR, RET to decodetree

Convert the simple (non-pointer-auth) BR, BLR and RET insns
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-18-peter.maydell@linaro.org


  Commit: 0ebbe9021254fb6db83780ac8b111e17b7ea2837
      
https://github.com/qemu/qemu/commit/0ebbe9021254fb6db83780ac8b111e17b7ea2837
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree

Convert the single-register pointer-authentication variants of BR,
BLR, RET to decodetree. (BRAA/BLRAA are in a different branch of
the legacy decoder and will be dealt with in the next commit.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-19-peter.maydell@linaro.org


  Commit: c990fde618c4ed2155c566fde0727bc3b6b7d119
      
https://github.com/qemu/qemu/commit/c990fde618c4ed2155c566fde0727bc3b6b7d119
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree

Convert the last four BR-with-pointer-auth insns to decodetree.
The remaining cases in the outer switch in disas_uncond_b_reg()
all return early rather than leaving the case statement, so we
can delete the now-unused code at the end of that function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-20-peter.maydell@linaro.org


  Commit: 442c9d682c94fc2e18014e6037735dcef7419a43
      
https://github.com/qemu/qemu/commit/442c9d682c94fc2e18014e6037735dcef7419a43
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert ERET, ERETAA, ERETAB to decodetree

Convert the exception-return insns ERET, ERETA and ERETB to
decodetree. These were the last insns left in the legacy
decoder function disas_uncond_reg_b(), which allows us to
remove it.

The old decoder explicitly decoded the DRPS instruction,
only in order to call unallocated_encoding() on it, exactly
as would have happened if it hadn't decoded it. This is
because this insn always UNDEFs unless the CPU is in
halting-debug state, which we don't emulate. So we list
the pattern in a comment in a64.decode, but don't actively
decode it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-21-peter.maydell@linaro.org


  Commit: 1aa4512ecde12372e51d2e94149854f952bd4211
      
https://github.com/qemu/qemu/commit/1aa4512ecde12372e51d2e94149854f952bd4211
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M target/arm/cortex-regs.c

  Log Message:
  -----------
  target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing

The IMPDEF sysreg L2CTLR_EL1 found on the Cortex-A35, A53, A57, A72
and which we (arguably dubiously) also provide in '-cpu max' has a
2 bit field for the number of processors in the cluster. On real
hardware this must be sufficient because it can only be configured
with up to 4 CPUs in the cluster. However on QEMU if the board code
does not explicitly configure the code into clusters with the right
CPU count we default to "give the value assuming that all CPUs in
the system are in a single cluster", which might be too big to fit
in the field.

Instead of just overflowing this 2-bit field, saturate to 3 (meaning
"4 CPUs", so at least we don't overwrite other fields in the register.
It's unlikely that any guest code really cares about the value in
this field; at least, if it does it probably also wants the system
to be more closely matching real hardware, i.e. not to have more
than 4 CPUs.

This issue has been present since the L2CTLR was first added in
commit 377a44ec8f2fac5b back in 2014. It was only noticed because
Coverity complains (CID 1509227) that the shift might overflow 32 bits
and inadvertently sign extend into the top half of the 64 bit value.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512170223.3801643-2-peter.maydell@linaro.org


  Commit: 18e8ba48f355bb03d56a248448100a3d5507cf66
      
https://github.com/qemu/qemu/commit/18e8ba48f355bb03d56a248448100a3d5507cf66
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M hw/arm/vexpress.c

  Log Message:
  -----------
  hw/arm/vexpress: Avoid trivial memory leak of 'flashalias'

In the vexpress board code, we allocate a new MemoryRegion at the top
of vexpress_common_init() but only set it up and use it inside the
"if (map[VE_NORFLASHALIAS] != -1)" conditional, so we leak it if not.
This isn't a very interesting leak as it's a tiny amount of memory
once at startup, but it's easy to fix.

We could silence Coverity simply by moving the g_new() into the
if() block, but this use of g_new(MemoryRegion, 1) is a legacy from
when this board model was originally written; we wouldn't do that
if we wrote it today. The MemoryRegions are conceptually a part of
the board and must not go away until the whole board is done with
(at the end of the simulation), so they belong in its state struct.

This machine already has a VexpressMachineState struct that extends
MachineState, so statically put the MemoryRegions in there instead of
dynamically allocating them separately at runtime.

Spotted by Coverity (CID 1509083).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230512170223.3801643-3-peter.maydell@linaro.org


  Commit: 91608e2a44f36e79cb83f863b8a7bb57d2c98061
      
https://github.com/qemu/qemu/commit/91608e2a44f36e79cb83f863b8a7bb57d2c98061
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M docs/system/device-emulation.rst
    A docs/system/devices/usb-u2f.rst
    M docs/system/devices/usb.rst
    R docs/u2f.txt

  Log Message:
  -----------
  docs: Convert u2f.txt to rST

Convert the u2f.txt file to rST, and place it in the right place
in our manual layout. The old text didn't fit very well into our
manual style, so the new version ends up looking like a rewrite,
although some of the original text is preserved:

 * the 'building' section of the old file is removed, since we
   generally assume that users have already built QEMU
 * some rather verbose text has been cut back
 * document the passthrough device first, on the assumption
   that's most likely to be of interest to users
 * cut back on the duplication of text between sections
 * format example command lines etc with rST

As it's a short document it seemed simplest to do this all
in one go rather than try to do a minimal syntactic conversion
and then clean up the wording and layout.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230421163734.1152076-1-peter.maydell@linaro.org


  Commit: 266ccbb27b3ec6661f22395ec2c41d854c94d761
      
https://github.com/qemu/qemu/commit/266ccbb27b3ec6661f22395ec2c41d854c94d761
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M MAINTAINERS
    M docs/system/device-emulation.rst
    A docs/system/devices/usb-u2f.rst
    M docs/system/devices/usb.rst
    R docs/u2f.txt
    M hw/arm/sbsa-ref.c
    M hw/arm/vexpress.c
    M hw/arm/virt.c
    M target/arm/cortex-regs.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/debug_helper.c
    M target/arm/kvm.c
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h
    A target/arm/tcg/a64.decode
    M target/arm/tcg/meson.build
    M target/arm/tcg/sve_helper.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20230518' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Fix vd == vm overlap in sve_ldff1_z
 * Add support for MTE with KVM guests
 * Add RAZ/WI handling for DBGDTR[TX|RX]
 * Start of conversion of A64 decoder to decodetree
 * Saturate L2CTLR_EL1 core count field rather than overflowing
 * vexpress: Avoid trivial memory leak of 'flashalias'
 * sbsa-ref: switch default cpu core to Neoverse-N1
 * sbsa-ref: use Bochs graphics card instead of VGA
 * MAINTAINERS: Add Marcin Juszkiewicz to sbsa-ref reviewer list
 * docs: Convert u2f.txt to rST

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# gpg: Signature made Thu 18 May 2023 05:49:55 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]

* tag 'pull-target-arm-20230518' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (29 commits)
  docs: Convert u2f.txt to rST
  hw/arm/vexpress: Avoid trivial memory leak of 'flashalias'
  target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing
  target/arm: Convert ERET, ERETAA, ERETAB to decodetree
  target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree
  target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree
  target/arm: Convert BR, BLR, RET to decodetree
  target/arm: Convert conditional branch insns to decodetree
  target/arm: Convert TBZ, TBNZ to decodetree
  target/arm: Convert CBZ, CBNZ to decodetree
  target/arm: Convert unconditional branch immediate to decodetree
  target/arm: Convert Extract instructions to decodetree
  target/arm: Convert Bitfield to decodetree
  target/arm: Convert Move wide (immediate) to decodetree
  target/arm: Convert Logical (immediate) to decodetree
  target/arm: Replace bitmask64 with MAKE_64BIT_MASK
  target/arm: Convert Add/subtract (immediate with tags) to decodetree
  target/arm: Convert Add/subtract (immediate) to decodetree
  target/arm: Split gen_add_CC and gen_sub_CC
  target/arm: Convert PC-rel addressing to decodetree
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/76ec63282cbf...266ccbb27b3e