[Qemu-commits] [qemu/qemu] fbea7a: accel/tcg: Unify cpu_{ld, st}*

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[Qemu-commits] [qemu/qemu] fbea7a: accel/tcg: Unify cpu_{ld, st}*_{be, l

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] fbea7a: accel/tcg: Unify cpu_{ld, st}*_{be, le}_mmu
Date:	Tue, 23 May 2023 18:58:23 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: fbea7a4084e54f3e604da0b4f8b36ac457d7efc8
      
https://github.com/qemu/qemu/commit/fbea7a4084e54f3e604da0b4f8b36ac457d7efc8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/cputlb.c
    M accel/tcg/ldst_common.c.inc
    M accel/tcg/tcg-runtime.h
    M accel/tcg/user-exec.c
    M include/exec/cpu_ldst.h
    M target/arm/tcg/m_helper.c
    M target/sparc/ldst_helper.c
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu

With the current structure of cputlb.c, there is no difference
between the little-endian and big-endian entry points, aside
from the assert.  Unify the pairs of functions.

The only use of the functions with explicit endianness was in
target/sparc64, and that was only to satisfy the assert: the
correct endianness is already built into memop.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ddc0ab5aab06554eeb67ddfe1ef6337035d7d084
      
https://github.com/qemu/qemu/commit/ddc0ab5aab06554eeb67ddfe1ef6337035d7d084
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M target/s390x/tcg/mem_helper.c

  Log Message:
  -----------
  target/s390x: Use cpu_{ld,st}*_mmu in do_csst

Use cpu_ld16_mmu and cpu_st16_mmu to eliminate the special case,
and change all of the *_data_ra functions to match.

Note that we check the alignment of both compare and store
pointers at the top of the function, so MO_ALIGN* may be
safely removed from the individual memory operations.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 47ae3e4039ff3d6b62219230dbead13a5fbbaea8
      
https://github.com/qemu/qemu/commit/47ae3e4039ff3d6b62219230dbead13a5fbbaea8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M target/s390x/tcg/mem_helper.c

  Log Message:
  -----------
  target/s390x: Always use cpu_atomic_cmpxchgl_be_mmu in do_csst

Eliminate the CONFIG_USER_ONLY specialization.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ec4a9629a14c45157d0e89daaff3c982df818cd6
      
https://github.com/qemu/qemu/commit/ec4a9629a14c45157d0e89daaff3c982df818cd6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/atomic_template.h
    M include/exec/cpu_ldst.h

  Log Message:
  -----------
  accel/tcg: Remove cpu_atomic_{ld,st}o_*_mmu

Atomic load/store of 128-byte quantities is now handled
by cpu_{ld,st}16_mmu.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7bedee3243b995281837a30ae7bf8982b4fd570c
      
https://github.com/qemu/qemu/commit/7bedee3243b995281837a30ae7bf8982b4fd570c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M accel/tcg/atomic_template.h
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c

  Log Message:
  -----------
  accel/tcg: Remove prot argument to atomic_mmu_lookup

Now that load/store are gone, we're always passing
PAGE_READ | PAGE_WRITE for RMW atomic operations.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4deb39ebb33d97e2ad5466e1b5b5e7c50ad83a0a
      
https://github.com/qemu/qemu/commit/4deb39ebb33d97e2ad5466e1b5b5e7c50ad83a0a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c
    M host/include/aarch64/host/atomic128-cas.h
    M host/include/generic/host/atomic128-ldst.h

  Log Message:
  -----------
  accel/tcg: Eliminate #if on HAVE_ATOMIC128 and HAVE_CMPXCHG128

These symbols will shortly become dynamic runtime tests and
therefore not appropriate for the preprocessor.  Use the
matching CONFIG_* symbols for that purpose.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 21c38f31c0f1d185feaefe39c367a12225b29089
      
https://github.com/qemu/qemu/commit/21c38f31c0f1d185feaefe39c367a12225b29089
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M host/include/aarch64/host/atomic128-ldst.h
    M host/include/generic/host/atomic128-ldst.h
    M target/s390x/tcg/mem_helper.c

  Log Message:
  -----------
  qemu/atomic128: Split atomic16_read

Create both atomic16_read_ro and atomic16_read_rw.
Previously we pretended that we had atomic16_read in system mode,
because we "know" that all ram is always writable to the host.
Now, expose read-only and read-write versions all of the time.

For aarch64, do not fall back to __atomic_read_16 even if
supported by the compiler, to work around a clang bug.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8dc24ff467c0d6f1166e229b3c297646ba06c19d
      
https://github.com/qemu/qemu/commit/8dc24ff467c0d6f1166e229b3c297646ba06c19d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/ldst_atomicity.c.inc

  Log Message:
  -----------
  accel/tcg: Correctly use atomic128.h in ldst_atomicity.c.inc

Remove the locally defined load_atomic16 and store_atomic16,
along with HAVE_al16 and HAVE_al16_fast in favor of the
routines defined in atomic128.h.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 427fbf3721da334c1f429d2a5285caa7025139c2
      
https://github.com/qemu/qemu/commit/427fbf3721da334c1f429d2a5285caa7025139c2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M MAINTAINERS
    A include/tcg/debug-assert.h
    M include/tcg/tcg.h

  Log Message:
  -----------
  tcg: Split out tcg/debug-assert.h

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b35b812567f090e41c4b194bb2a752f29e9aedcc
      
https://github.com/qemu/qemu/commit/b35b812567f090e41c4b194bb2a752f29e9aedcc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M host/include/generic/host/atomic128-ldst.h

  Log Message:
  -----------
  qemu/atomic128: Improve cmpxchg fallback for atomic16_set

Use __sync_bool_compare_and_swap_16 to control the loop,
rather than a separate comparison.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e45fb74ddb75913f81a48112b828ee58bd9f6e2a
      
https://github.com/qemu/qemu/commit/e45fb74ddb75913f81a48112b828ee58bd9f6e2a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M host/include/aarch64/host/atomic128-ldst.h

  Log Message:
  -----------
  qemu/atomic128: Add runtime test for FEAT_LSE2

With FEAT_LSE2, load and store of int128 is directly supported.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 645e3a812a3837808066df22dc78bacb2e3d14c6
      
https://github.com/qemu/qemu/commit/645e3a812a3837808066df22dc78bacb2e3d14c6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M accel/tcg/cpu-exec.c
    M accel/tcg/translate-all.c
    M accel/tcg/translator.c
    M include/exec/exec-all.h
    M target/sh4/translate.c
    M target/sparc/translate.c
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Remove DEBUG_DISAS

This had been set since the beginning, is never undefined,
and it would seem to be harmful to debugging to do so.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 16ffa1ef87c58a9a13d0ed5b3afe8c2a0d322e93
      
https://github.com/qemu/qemu/commit/16ffa1ef87c58a9a13d0ed5b3afe8c2a0d322e93
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Remove USE_TCG_OPTIMIZATIONS

This is always defined, and the optimization pass is
essential to producing reasonable code.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1c12355b31046a6b35a4f50c85c4f01afb1bd728
      
https://github.com/qemu/qemu/commit/1c12355b31046a6b35a4f50c85c4f01afb1bd728
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M MAINTAINERS
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/atomic_template.h
    M accel/tcg/cpu-exec.c
    M accel/tcg/cputlb.c
    M accel/tcg/ldst_atomicity.c.inc
    M accel/tcg/ldst_common.c.inc
    M accel/tcg/tcg-runtime.h
    M accel/tcg/translate-all.c
    M accel/tcg/translator.c
    M accel/tcg/user-exec.c
    A host/include/aarch64/host/atomic128-cas.h
    A host/include/aarch64/host/atomic128-ldst.h
    A host/include/aarch64/host/cpuinfo.h
    A host/include/generic/host/atomic128-cas.h
    A host/include/generic/host/atomic128-ldst.h
    A host/include/generic/host/cpuinfo.h
    A host/include/i386/host/cpuinfo.h
    A host/include/x86_64/host/cpuinfo.h
    M include/exec/cpu_ldst.h
    M include/exec/exec-all.h
    M include/qemu/atomic128.h
    A include/tcg/debug-assert.h
    M include/tcg/tcg.h
    M meson.build
    M migration/meson.build
    M migration/ram.c
    M migration/xbzrle.c
    M migration/xbzrle.h
    M target/arm/tcg/m_helper.c
    M target/ppc/cpu.h
    M target/ppc/helper.h
    M target/ppc/mem_helper.c
    M target/ppc/translate.c
    M target/ppc/translate/fixedpoint-impl.c.inc
    M target/s390x/cpu.h
    M target/s390x/helper.h
    M target/s390x/tcg/insn-data.h.inc
    M target/s390x/tcg/mem_helper.c
    M target/s390x/tcg/translate.c
    M target/sh4/translate.c
    M target/sparc/ldst_helper.c
    M target/sparc/translate.c
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h
    M tcg/tcg-op-ldst.c
    M tcg/tcg.c
    M tests/bench/meson.build
    R tests/bench/xbzrle-bench.c
    M tests/unit/test-xbzrle.c
    M util/bufferiszero.c
    A util/cpuinfo-aarch64.c
    A util/cpuinfo-i386.c
    M util/meson.build

  Log Message:
  -----------
  Merge tag 'pull-tcg-20230523-3' of https://gitlab.com/rth7680/qemu into 
staging

util: Host cpu detection for x86 and aa64
util: Use cpu detection for bufferiszero
migration: Use cpu detection for xbzrle
tcg: Replace and remove cpu_atomic_{ld,st}o*
host/include: Split qemu/atomic128.h
tcg: Remove DEBUG_DISAS
tcg: Remove USE_TCG_OPTIMIZATIONS

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[ultimate]

* tag 'pull-tcg-20230523-3' of https://gitlab.com/rth7680/qemu: (28 commits)
  tcg: Remove USE_TCG_OPTIMIZATIONS
  tcg: Remove DEBUG_DISAS
  qemu/atomic128: Add runtime test for FEAT_LSE2
  qemu/atomic128: Improve cmpxchg fallback for atomic16_set
  tcg: Split out tcg/debug-assert.h
  accel/tcg: Correctly use atomic128.h in ldst_atomicity.c.inc
  qemu/atomic128: Split atomic16_read
  accel/tcg: Eliminate #if on HAVE_ATOMIC128 and HAVE_CMPXCHG128
  accel/tcg: Remove prot argument to atomic_mmu_lookup
  accel/tcg: Remove cpu_atomic_{ld,st}o_*_mmu
  target/s390x: Always use cpu_atomic_cmpxchgl_be_mmu in do_csst
  target/s390x: Use cpu_{ld,st}*_mmu in do_csst
  accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu
  target/s390x: Use tcg_gen_qemu_{ld,st}_i128 for LPQ, STPQ
  target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQ
  include/qemu: Move CONFIG_ATOMIC128_OPT handling to atomic128.h
  meson: Fix detect atomic128 support with optimization
  include/host: Split out atomic128-ldst.h
  include/host: Split out atomic128-cas.h
  util: Add cpuinfo-aarch64.c
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/e5e4adf11137...1c12355b3104
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