[Qemu-commits] [qemu/qemu] 5260ec: target/ppc: Fix fallback to MFSS for MFFS* instruc...

[Richard Henderson]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 5260ecffd24e36c029849f379c8b9cc3d099c879
      
https://github.com/qemu/qemu/commit/5260ecffd24e36c029849f379c8b9cc3d099c879
  Author: Richard Purdie <richard.purdie@linuxfoundation.org>
  Date:   2023-05-27 (Sat, 27 May 2023)

  Changed paths:
    M target/ppc/insn32.decode
    M target/ppc/translate/fp-impl.c.inc

  Log Message:
  -----------
  target/ppc: Fix fallback to MFSS for MFFS* instructions on pre 3.0 ISAs

The following commits changed the code such that the fallback to MFSS for 
MFFSCRN,
MFFSCRNI, MFFSCE and MFFSL on pre 3.0 ISAs was removed and became an illegal 
instruction:

  bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to 
decodetree
  394c2e2fda70da722f20fb60412d6c0ca4bfaa03 - target/ppc: Move mffsce to 
decodetree
  3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to 
decodetree

The hardware will handle them as a MFFS instruction as the code did previously.
This means applications that were segfaulting under qemu when encountering these
instructions which is used in glibc libm functions for example.

The fallback for MFFSCDRN and MFFSCDRNI added in a later patch was also missing.

This patch restores the fallback to MFSS for these instructions on pre 3.0s ISAs
as the hardware decoder would, fixing the segfaulting libm code. It doesn't have
the fallback for 3.0 onwards to match hardware behaviour.

Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230510111913.1718734-1-richard.purdie@linuxfoundation.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: fbda88f7abdeed3ceebdd18de6909a52df756c1c
      
https://github.com/qemu/qemu/commit/fbda88f7abdeed3ceebdd18de6909a52df756c1c
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2023-05-27 (Sat, 27 May 2023)

  Changed paths:
    M target/ppc/cpu_init.c
    M target/ppc/helper_regs.c
    M target/ppc/misc_helper.c
    M target/ppc/power8-pmu.c
    M target/ppc/spr_common.h
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Fix width of some 32-bit SPRs

Some 32-bit SPRs are incorrectly implemented as 64-bits on 64-bit
targets.

This changes VRSAVE, DSISR, HDSISR, DAWRX0, PIDR, LPIDR, DEXCR,
HDEXCR, CTRL, TSCR, MMCRH, and PMC[1-6] from to be 32-bit registers.

This only goes by the 32/64 classification in the architecture, it
does not try to implement finer details of SPR implementation (e.g.,
not all bits implemented as simple read/write storage).

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Message-Id: <20230515092655.171206-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 4ee5d2817ff18d10be887853d5e966247f0a0c30
      
https://github.com/qemu/qemu/commit/4ee5d2817ff18d10be887853d5e966247f0a0c30
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2023-05-27 (Sat, 27 May 2023)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward

This optional behavior was removed from the ISA in v3.0, see
Summary of Changes preface:

  Data Storage Interrupt Status Register for Alignment Interrupt:
  Simplifies the Alignment interrupt by remov- ing the Data Storage
  Interrupt Status Register (DSISR) from the set of registers modified
  by the Alignment interrupt.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230515092655.171206-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: ccc5a4c5e108775667ffc25182cd2ba2326ac979
      
https://github.com/qemu/qemu/commit/ccc5a4c5e108775667ffc25182cd2ba2326ac979
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2023-05-28 (Sun, 28 May 2023)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_hcall.c
    M include/hw/ppc/spapr.h
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h

  Log Message:
  -----------
  spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcall

The behaviour of the Address Translation Mode on Interrupt resource is
not consistently supported by all CPU versions or all KVM versions: KVM
HV does not support mode 2, and does not support mode 3 on POWER7 or
early POWER9 processesors. KVM PR only supports mode 0. TCG supports all
modes (0, 2, 3) on CPUs with support for the corresonding LPCR[AIL] mode.
This leads to inconsistencies in guest behaviour and could cause problems
migrating guests.

This was not noticable for Linux guests for a long time because the
kernel only uses modes 0 and 3, and it used to consider AIL-3 to be
advisory in that it would always keep the AIL-0 vectors around, so it
did not matter whether or not interrupts were delivered according to
the AIL mode. Recent Linux guests depend on AIL mode 3 working as
specified in order to support the SCV facility interrupt. If AIL-3 can
not be provided, then H_SET_MODE must return an error to Linux so it can
disable the SCV facility (failure to do so can lead to userspace being
able to crash the guest kernel).

Add the ail-mode-3 capability to specify that AIL-3 is supported. AIL-0
is implied as the baseline, and AIL-2 is no longer supported by spapr.
AIL-2 is not known to be used by any software, but support in TCG could
be restored with an ail-mode-2 capability quite easily if a regression
is reported.

Modify the H_SET_MODE Address Translation Mode on Interrupt resource
handler to check capabilities and correctly return error if not
supported.

KVM has a cap to advertise support for AIL-3.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230515160216.394612-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 2237af5e60ada06d90bf714e85523deafd936b9b
      
https://github.com/qemu/qemu/commit/2237af5e60ada06d90bf714e85523deafd936b9b
  Author: Bernhard Beschow <shentey@gmail.com>
  Date:   2023-05-28 (Sun, 28 May 2023)

  Changed paths:
    M hw/ppc/prep.c

  Log Message:
  -----------
  hw/ppc/prep: Fix wiring of PIC -> CPU interrupt

Commit cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder")
passes s->cpu_intr to i8259_init() in i82378_realize() directly. However, s-
>cpu_intr isn't initialized yet since that happens after the south bridge's
pci_realize_and_unref() in board code. Fix this by initializing s->cpu_intr
before realizing the south bridge.

Fixes: cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder")
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230304114043.121024-4-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 7f65ebb0e79b43602d516aa29f9b13ccc7224d52
      
https://github.com/qemu/qemu/commit/7f65ebb0e79b43602d516aa29f9b13ccc7224d52
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2023-05-28 (Sun, 28 May 2023)

  Changed paths:
    M target/ppc/cpu-models.h

  Log Message:
  -----------
  target/ppc: Use SMT4 small core chip type in POWER9/10 PVRs

QEMU's PVR value for POWER9 DD2.0 has chip type 1, which is the SMT4
"small core" type that OpenPOWER processors use. QEMU's PVR for all
other POWER9/10 have chip type 0, which "enterprise" systems use.

The difference does not really matter to QEMU (because it does not care
about SMT mode in the target), but for consistency all PVRs should use
the same chip type. We'll go with the SMT4 OpenPOWER type.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230515160131.394562-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 76f9ebffcd41b62ae9ec26a1c25676f2ae1d9cc3
      
https://github.com/qemu/qemu/commit/76f9ebffcd41b62ae9ec26a1c25676f2ae1d9cc3
  Author: Alexander Bulekov <alxndr@bu.edu>
  Date:   2023-05-28 (Sun, 28 May 2023)

  Changed paths:
    M hw/ppc/pnv_lpc.c

  Log Message:
  -----------
  pnv_lpc: disable reentrancy detection for lpc-hc

As lpc-hc is designed for re-entrant calls from xscom, mark it
re-entrancy safe.

Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alexander Bulekov <alxndr@bu.edu>
[clg: mark opb_master_regs as re-entrancy safe also ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230526073850.2772197-1-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 03ec9d9d22bb7ec81f35c1c34249d2989e7a74b4
      
https://github.com/qemu/qemu/commit/03ec9d9d22bb7ec81f35c1c34249d2989e7a74b4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-28 (Sun, 28 May 2023)

  Changed paths:
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  target/ppc: Merge COMPUTE_CLASS and COMPUTE_FPRF

Instead of computing an artificial "class" bitmask then converting that
to the fprf value, compute the final value from the start.

Reorder the tests to check the most likely cases first.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230523202507.688859-1-richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 277ee17212f0ac965d1fb7d65d8f938a790229ad
      
https://github.com/qemu/qemu/commit/277ee17212f0ac965d1fb7d65d8f938a790229ad
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2023-05-28 (Sun, 28 May 2023)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/pnv_core.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M include/hw/ppc/pnv.h
    M target/ppc/cpu-models.c
    M target/ppc/cpu-models.h
    M target/ppc/cpu_init.c
    M tests/qtest/device-plug-test.c

  Log Message:
  -----------
  target/ppc: Add POWER9 DD2.2 model

POWER9 DD2.1 and earlier had significant limitations when running KVM,
including lack of "mixed mode" MMU support (ability to run HPT and RPT
mode on threads of the same core), and a translation prefetch issue
which is worked around by disabling "AIL" mode for the guest.

These processors are not widely available, and it's difficult to deal
with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU
and make it the default POWER9 CPU.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Message-Id: <20230515160201.394587-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: 56b8bfe9bb6b94184b8bbfc4be9196404a81e450
      
https://github.com/qemu/qemu/commit/56b8bfe9bb6b94184b8bbfc4be9196404a81e450
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2023-05-28 (Sun, 28 May 2023)

  Changed paths:
    M hw/ppc/pegasos2.c

  Log Message:
  -----------
  ppc/pegasos2: Change default CPU to 7457

Previously 7400 was selected as a safe choice as that is used by other
machines so it's better tested but AmigaOS does not know this CPU and
disables some features when running on it. The real hardware has
7447/7457 G4 CPU so change the default to match that now that it was
confirmed to work better with AmigaOS.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230528152937.B8DAD74633D@zero.eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>


  Commit: aa9bbd865502ed517624ab6fe7d4b5d89ca95e43
      
https://github.com/qemu/qemu/commit/aa9bbd865502ed517624ab6fe7d4b5d89ca95e43
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-29 (Mon, 29 May 2023)

  Changed paths:
    M hw/ppc/pegasos2.c
    M hw/ppc/pnv.c
    M hw/ppc/pnv_core.c
    M hw/ppc/pnv_lpc.c
    M hw/ppc/prep.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_hcall.c
    M include/hw/ppc/pnv.h
    M include/hw/ppc/spapr.h
    M target/ppc/cpu-models.c
    M target/ppc/cpu-models.h
    M target/ppc/cpu_init.c
    M target/ppc/excp_helper.c
    M target/ppc/fpu_helper.c
    M target/ppc/helper_regs.c
    M target/ppc/insn32.decode
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h
    M target/ppc/misc_helper.c
    M target/ppc/power8-pmu.c
    M target/ppc/spr_common.h
    M target/ppc/translate.c
    M target/ppc/translate/fp-impl.c.inc
    M tests/qtest/device-plug-test.c

  Log Message:
  -----------
  Merge tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2023-05-28:

This queue includes several assorted fixes for PowerPC SPR
emulation, a change in the default Pegasos2 CPU, the addition
of AIL mode 3 for spapr, a PIC->CPU interrupt fix for prep and
performance enhancements in fpu_helper.c.

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# gpg: Signature made Sun 28 May 2023 09:47:05 AM PDT
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# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" 
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* tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu:
  ppc/pegasos2: Change default CPU to 7457
  target/ppc: Add POWER9 DD2.2 model
  target/ppc: Merge COMPUTE_CLASS and COMPUTE_FPRF
  pnv_lpc: disable reentrancy detection for lpc-hc
  target/ppc: Use SMT4 small core chip type in POWER9/10 PVRs
  hw/ppc/prep: Fix wiring of PIC -> CPU interrupt
  spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcall
  target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward
  target/ppc: Fix width of some 32-bit SPRs
  target/ppc: Fix fallback to MFSS for MFFS* instructions on pre 3.0 ISAs

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/57b93c0f8ea3...aa9bbd865502