[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 21eb5b: hw/arm/smmuv3: Parse STE config for s
|
From: |
Richard Henderson |
|
Subject: |
[Qemu-commits] [qemu/qemu] 21eb5b: hw/arm/smmuv3: Parse STE config for stage-2 |
|
Date: |
Tue, 30 May 2023 08:02:52 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 21eb5b5cde7f6f75751837d3082ce8b36070af33
https://github.com/qemu/qemu/commit/21eb5b5cde7f6f75751837d3082ce8b36070af33
Author: Mostafa Saleh <smostafa@google.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M include/hw/arm/smmu-common.h
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3: Parse STE config for stage-2
Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
Validity of field values are checked when possible.
Only AA64 tables are supported and Small Translation Tables (STT) are
not supported.
According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields
with an S2 prefix (with the exception of S2VMID) are IGNORED when
stage-2 bypasses translation (Config[1] == 0).
Which means that VMID can be used(for TLB tagging) even if stage-2 is
bypassed, so we parse it unconditionally when S2P exists. Otherwise
it is set to -1.(only S1P)
As stall is not supported, if S2S is set the translation would abort.
For S2R, we reuse the same code used for stage-1 with flag
record_faults. However when nested translation is supported we would
need to separate stage-1 and stage-2 faults.
Fix wrong shift in STE_S2HD, STE_S2HA, STE_S2S.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230516203327.2051088-6-smostafa@google.com
[PMM: fixed format string]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cd617556aded2528664a3673d66d5cd0864f5341
https://github.com/qemu/qemu/commit/cd617556aded2528664a3673d66d5cd0864f5341
Author: Mostafa Saleh <smostafa@google.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Make TLB lookup work for stage-2
Right now, either stage-1 or stage-2 are supported, this simplifies
how we can deal with TLBs.
This patch makes TLB lookup work if stage-2 is enabled instead of
stage-1.
TLB lookup is done before a PTW, if a valid entry is found we won't
do the PTW.
To be able to do TLB lookup, we need the correct tagging info, as
granularity and input size, so we get this based on the supported
translation stage. The TLB entries are added correctly from each
stage PTW.
When nested translation is supported, this would need to change, for
example if we go with a combined TLB implementation, we would need to
use the min of the granularities in TLB.
As stage-2 shouldn't be tagged by ASID, it will be set to -1 if S1P
is not enabled.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-7-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2eaeb7d593254a34f3e551865b687886c2698f96
https://github.com/qemu/qemu/commit/2eaeb7d593254a34f3e551865b687886c2698f96
Author: Mostafa Saleh <smostafa@google.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmu-internal.h
M hw/arm/smmuv3.c
M hw/arm/trace-events
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmuv3: Add VMID to TLB tagging
Allow TLB to be tagged with VMID.
If stage-1 is only supported, VMID is set to -1 and ignored from STE
and CMD_TLBI_NH* cmds.
Update smmu_iotlb_insert trace event to have vmid.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-8-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ccc3ee38713381a823a6b9229b36a0a1b36d919d
https://github.com/qemu/qemu/commit/ccc3ee38713381a823a6b9229b36a0a1b36d919d
Author: Mostafa Saleh <smostafa@google.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M hw/arm/trace-events
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmuv3: Add CMDs related to stage-2
CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
same as CMD_TLBI_NH_VAA.
CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.
For stage-1 only commands, add a check to throw CERROR_ILL if used
when stage-1 is not supported.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-9-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 32bd7baec2991bba1d801c348a74fc531dcae6f1
https://github.com/qemu/qemu/commit/32bd7baec2991bba1d801c348a74fc531dcae6f1
Author: Mostafa Saleh <smostafa@google.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M hw/arm/smmuv3.c
M hw/arm/trace-events
Log Message:
-----------
hw/arm/smmuv3: Add stage-2 support in iova notifier
In smmuv3_notify_iova, read the granule based on translation stage
and use VMID if valid value is sent.
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-10-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8cefcc3b7127f1c497aa832378fe69453fb9db2c
https://github.com/qemu/qemu/commit/8cefcc3b7127f1c497aa832378fe69453fb9db2c
Author: Mostafa Saleh <smostafa@google.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M hw/arm/smmuv3.c
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2
As everything is in place, we can use a new system property to
advertise which stage is supported and remove bad_ste from STE
stage2 config.
The property added arm-smmuv3.stage can have 3 values:
- "1": Stage-1 only is advertised.
- "2": Stage-2 only is advertised.
If not passed or an unsupported value is passed, it will default to
stage-1.
Advertise VMID16.
Don't try to decode CD, if stage-2 is configured.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230516203327.2051088-11-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 31afe04586efeccb80cc36ffafcd0e32a3245ffb
https://github.com/qemu/qemu/commit/31afe04586efeccb80cc36ffafcd0e32a3245ffb
Author: Tommy Wu <tommy.wu@sifive.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M hw/dma/xilinx_axidma.c
Log Message:
-----------
hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.
When we receive a packet from the xilinx_axienet and then try to s2mem
through the xilinx_axidma, if the descriptor ring buffer is full in the
xilinx axidma driver, we’ll assert the DMASR.HALTED in the
function : stream_process_s2mem and return 0. In the end, we’ll be stuck in
an infinite loop in axienet_eth_rx_notify.
This patch checks the DMASR.HALTED state when we try to push data
from xilinx axi-enet to xilinx axi-dma. When the DMASR.HALTED is asserted,
we will not keep pushing the data and then prevent the infinte loop.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20230519062137.1251741-1-tommy.wu@sifive.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c9ba1c9f02cfede5329f504cdda6fd3a256e0434
https://github.com/qemu/qemu/commit/c9ba1c9f02cfede5329f504cdda6fd3a256e0434
Author: Clément Chigot <chigot@adacore.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M hw/arm/xlnx-zynqmp.c
Log Message:
-----------
hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
When passing --smp with a number lower than XLNX_ZYNQMP_NUM_APU_CPUS,
the expression (ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS) will result
in a positive number as ms->smp.cpus is a unsigned int.
This will raise the following error afterwards, as Qemu will try to
instantiate some additional RPUs.
| $ qemu-system-aarch64 --smp 1 -M xlnx-zcu102
| **
| ERROR:../src/tcg/tcg.c:777:tcg_register_thread:
| assertion failed: (n < tcg_max_ctxs)
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20230524143714.565792-1-chigot@adacore.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e19d24e6d91ec92383c989d942c61a91b2a6bdac
https://github.com/qemu/qemu/commit/e19d24e6d91ec92383c989d942c61a91b2a6bdac
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest: Run arm-specific tests only if the required machine is available
pflash-cfi02-test.c always uses the "musicpal" machine for testing,
test-arm-mptimer.c always uses the "vexpress-a9" machine, and
microbit-test.c requires the "microbit" machine, so we should only
run these tests if the machines have been enabled in the configuration.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230524080600.1618137-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d7fe699be54b2cbb8e4ee37b63588b3458a49da7
https://github.com/qemu/qemu/commit/d7fe699be54b2cbb8e4ee37b63588b3458a49da7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M target/arm/tcg/tlb_helper.c
Log Message:
-----------
target/arm: Explicitly select short-format FSR for M-profile
For M-profile, there is no guest-facing A-profile format FSR, but we
still use the env->exception.fsr field to pass fault information from
the point where a fault is raised to the code in
arm_v7m_cpu_do_interrupt() which interprets it and sets the M-profile
specific fault status registers. So it doesn't matter whether we
fill in env->exception.fsr in the short format or the LPAE format, as
long as both sides agree. As it happens arm_v7m_cpu_do_interrupt()
assumes short-form.
In compute_fsr_fsc() we weren't explicitly choosing short-form for
M-profile, but instead relied on it falling out in the wash because
arm_s1_regime_using_lpae_format() would be false. This was broken in
commit 452c67a4 when we added v8R support, because we said "PMSAv8 is
always LPAE format" (as it is for v8R), forgetting that we were
implicitly using this code path on M-profile. At that point we would
hit a g_assert_not_reached():
ERROR:../../target/arm/internals.h:549:arm_fi_to_lfsc: code should not be
reached
#7 0x0000555555e055f7 in arm_fi_to_lfsc (fi=0x7fffecff9a90) at
../../target/arm/internals.h:549
#8 0x0000555555e05a27 in compute_fsr_fsc (env=0x555557356670,
fi=0x7fffecff9a90, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff9a1c)
at ../../target/arm/tlb_helper.c:95
#9 0x0000555555e05b62 in arm_deliver_fault (cpu=0x555557354800,
addr=268961344, access_type=MMU_INST_FETCH, mmu_idx=1, fi=0x7fffecff9a90)
at ../../target/arm/tlb_helper.c:132
#10 0x0000555555e06095 in arm_cpu_tlb_fill (cs=0x555557354800,
address=268961344, size=1, access_type=MMU_INST_FETCH, mmu_idx=1, probe=false,
retaddr=0)
at ../../target/arm/tlb_helper.c:260
The specific assertion changed when commit fcc7404eff24b4c added
"assert not M-profile" to arm_is_secure_below_el3(), because the
conditions being checked in compute_fsr_fsc() include
arm_el_is_aa64(), which will end up calling arm_is_secure_below_el3()
and asserting before we try to call arm_fi_to_lfsc():
#7 0x0000555555efaf43 in arm_is_secure_below_el3 (env=0x5555574665a0) at
../../target/arm/cpu.h:2396
#8 0x0000555555efb103 in arm_is_el2_enabled (env=0x5555574665a0) at
../../target/arm/cpu.h:2448
#9 0x0000555555efb204 in arm_el_is_aa64 (env=0x5555574665a0, el=1) at
../../target/arm/cpu.h:2509
#10 0x0000555555efbdfd in compute_fsr_fsc (env=0x5555574665a0,
fi=0x7fffecff99e0, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff996c)
Avoid the assertion and the incorrect FSR format selection by
explicitly making M-profile use the short-format in this function.
Fixes: 452c67a42704 ("target/arm: Enable TTBCR_EAE for ARMv8-R AArch32")a
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1658
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230523131726.866635-1-peter.maydell@linaro.org
Commit: 257a5ec524374bd00da38b30dddfef1d96ca96f4
https://github.com/qemu/qemu/commit/257a5ec524374bd00da38b30dddfef1d96ca96f4
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M target/arm/Kconfig
Log Message:
-----------
target/arm: Explain why we need to select ARM_V7M
We currently need to select ARM_V7M unconditionally when TCG is
present in the build because some translate.c helpers and the whole of
m_helpers.c are not yet under CONFIG_ARM_V7M.
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230523180525.29994-2-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: da324efb179cc86e6c8751a59dc215e510836b6d
https://github.com/qemu/qemu/commit/da324efb179cc86e6c8751a59dc215e510836b6d
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M configs/devices/aarch64-softmmu/default.mak
M configs/devices/arm-softmmu/default.mak
Log Message:
-----------
arm/Kconfig: Keep Kconfig default entries in default.mak as documentation
When we moved the arm default CONFIGs into Kconfig and removed them
from default.mak, we made it harder to identify which CONFIGs are
selected by default in case users want to disable them.
Bring back the default entries into default.mak, but keep them
commented out. This way users can keep their workflows of editing
default.mak to remove build options without needing to search through
Kconfig.
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230523180525.29994-3-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 441d701db75a6aa0c5e7c21836282e1555924a2d
https://github.com/qemu/qemu/commit/441d701db75a6aa0c5e7c21836282e1555924a2d
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M hw/arm/Kconfig
Log Message:
-----------
arm/Kconfig: Make TCG dependence explicit
Replace the 'default y if TCG' pattern with 'default y; depends on
TCG'.
That makes explict that there is a dependence on TCG and enabling
these CONFIGs via .mak files without TCG present will fail earlier.
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230523180525.29994-4-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5d6c687c9d2249de3f41d8d71baa1f15cc5cf112
https://github.com/qemu/qemu/commit/5d6c687c9d2249de3f41d8d71baa1f15cc5cf112
Author: Enze Li <lienze@kylinos.cn>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M docs/conf.py
M include/qemu/help-texts.h
Log Message:
-----------
Update copyright dates to 2023
I noticed that in the latest version, the copyright string is still
2022, even though 2023 is halfway through. This patch fixes that and
fixes the documentation along with it.
Signed-off-by: Enze Li <lienze@kylinos.cn>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230525064345.1152801-1-lienze@kylinos.cn
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0c08d4f310ebf3f621ee5b7447ded0736decbb43
https://github.com/qemu/qemu/commit/0c08d4f310ebf3f621ee5b7447ded0736decbb43
Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm/sbsa-ref: add GIC node into DT
Let add GIC information into DeviceTree as part of SBSA-REF versioning.
Trusted Firmware will read it and provide to next firmware level.
Bumps platform version to 0.1 one so we can check is node is present.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ec683110def96b16be3931ec87baba65a3dc5ad0
https://github.com/qemu/qemu/commit/ec683110def96b16be3931ec87baba65a3dc5ad0
Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M docs/system/arm/sbsa.rst
Log Message:
-----------
docs: sbsa: correct graphics card name
We moved from VGA to Bochs to have PCIe card.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7fe6cb68117ac856e03c93d18aca09de015392b0
https://github.com/qemu/qemu/commit/7fe6cb68117ac856e03c93d18aca09de015392b0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-30 (Tue, 30 May 2023)
Changed paths:
M configs/devices/aarch64-softmmu/default.mak
M configs/devices/arm-softmmu/default.mak
M docs/conf.py
M docs/system/arm/sbsa.rst
M hw/arm/Kconfig
M hw/arm/fsl-imx6.c
M hw/arm/sbsa-ref.c
M hw/arm/smmu-common.c
M hw/arm/smmu-internal.h
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M hw/arm/trace-events
M hw/arm/xlnx-zynqmp.c
M hw/dma/xilinx_axidma.c
M include/hw/arm/fsl-imx6.h
M include/hw/arm/smmu-common.h
M include/hw/arm/smmuv3.h
M include/qemu/help-texts.h
M target/arm/Kconfig
M target/arm/tcg/tlb_helper.c
M tests/qtest/meson.build
Log Message:
-----------
Merge tag 'pull-target-arm-20230530-1' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* fsl-imx6: Add SNVS support for i.MX6 boards
* smmuv3: Add support for stage 2 translations
* hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop
* hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
* cleanups for recent Kconfig changes
* target/arm: Explicitly select short-format FSR for M-profile
* tests/qtest: Run arm-specific tests only if the required machine is available
* hw/arm/sbsa-ref: add GIC node into DT
* docs: sbsa: correct graphics card name
* Update copyright dates to 2023
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmR2DYsZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3ubED/40MFaRWfJuVhD3NzWltzhD
# 5Y2/kxd3Bm51ki56hiBWXBXeovR3Exve9rP8OOGJ5RUK0SoEb4xdIjwMAGRt1Ksi
# Ln4MUqjv0tqUNv1hBDKgnGJ4dW34bhmJAnU/Jdzt8yrpGuSmN+LCWoPC+vTNCWYm
# sNFm8VLB+nmVq/sjTKwQc/Uo+7l9JZ+aY6poyHfN7kKpITUHtoCPgwz34btRrXEk
# 4+eNYQV1UvofRhLRVsIrvA89bd7Rcn5iHbhY+xYHaJDEaoYy7iBfUJeDlUtEgW8k
# 0fXt5Z5bXUXpz7jmzXdbq//68p8HcqinarIFH4r0Nbu+u2UgkZDJZRns+p5i8Wmv
# qE+hLGOgEg8s9n2e6chGuvw6wX49T3Xtr7tNpKQfi5ou5VT7qZIwl50m/JefuoPI
# eHu4uPj7pS0z/s8KDk0mNtbfcHkzmT5KpZkbvS2JOzg9o2t1fwGCbKPlcgJPxcIV
# Ro7R3rNvd6XSSQBlmcYNXWE7P7zuJyfjfSN7D7b0MdFP/hBTpLGKI2LBggZEdcce
# 21fiEkEE6d1L2oN+Eiq3q8xQNoVjYSGaE5LJ34+997z7W1JRB/dyJhZM0AkabSMl
# mkgyi9kBKxU4S9pxtZ//Uh9B/5blpMQAI4U8S/svuGqzwfI6luY/Qxue+YzRUD0H
# XsDSBnq1x2LW2Fhu7YVW3Q==
# =/OdY
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 30 May 2023 07:51:55 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
* tag 'pull-target-arm-20230530-1' of
https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits)
docs: sbsa: correct graphics card name
hw/arm/sbsa-ref: add GIC node into DT
Update copyright dates to 2023
arm/Kconfig: Make TCG dependence explicit
arm/Kconfig: Keep Kconfig default entries in default.mak as documentation
target/arm: Explain why we need to select ARM_V7M
target/arm: Explicitly select short-format FSR for M-profile
tests/qtest: Run arm-specific tests only if the required machine is available
hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.
hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2
hw/arm/smmuv3: Add stage-2 support in iova notifier
hw/arm/smmuv3: Add CMDs related to stage-2
hw/arm/smmuv3: Add VMID to TLB tagging
hw/arm/smmuv3: Make TLB lookup work for stage-2
hw/arm/smmuv3: Parse STE config for stage-2
hw/arm/smmuv3: Add page table walk for stage-2
hw/arm/smmuv3: Refactor stage-1 PTW
hw/arm/smmuv3: Update translation config to hold stage-2
hw/arm/smmuv3: Add missing fields for IDR0
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/f1be1eafdc78...7fe6cb68117a
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] 21eb5b: hw/arm/smmuv3: Parse STE config for stage-2,
Richard Henderson <=