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[Qemu-commits] [qemu/qemu] 20b42c: target/arm: Move some register relate
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 20b42c: target/arm: Move some register related defines to ... |
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Date: |
Fri, 08 Mar 2024 10:20:04 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 20b42c331df544a6d889f4bcf4535c0f2f98dbcf
https://github.com/qemu/qemu/commit/20b42c331df544a6d889f4bcf4535c0f2f98dbcf
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/internals.h
Log Message:
-----------
target/arm: Move some register related defines to internals.h
cpu.h has a lot of #defines relating to CPU register fields.
Most of these aren't actually used outside target/arm code,
so there's no point in cluttering up the cpu.h file with them.
Move some easy ones to internals.h.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-2-peter.maydell@linaro.org
Commit: 1e8d14037bff6c235917340177c5f9977c564ec0
https://github.com/qemu/qemu/commit/1e8d14037bff6c235917340177c5f9977c564ec0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Timer _EL02 registers UNDEF for E2H == 0
The timer _EL02 registers should UNDEF for invalid accesses from EL2
or EL3 when HCR_EL2.E2H == 0, not take a cp access trap. We were
delivering the exception to EL2 with the wrong syndrome.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-3-peter.maydell@linaro.org
Commit: c6b0ecb236ba6f8c29cf00c93494901aa22e4dae
https://github.com/qemu/qemu/commit/c6b0ecb236ba6f8c29cf00c93494901aa22e4dae
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: use FIELD macro for CNTHCTL bit definitions
We prefer the FIELD macro over ad-hoc #defines for register bits;
switch CNTHCTL to that style before we add any more bits.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org
Commit: a681d66e95f0eb5de014fbbc8f1d6286e0750bb5
https://github.com/qemu/qemu/commit/a681d66e95f0eb5de014fbbc8f1d6286e0750bb5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
Don't allow the guest to write CNTHCTL_EL2 bits which don't exist.
This is not strictly architecturally required, but it is how we've
tended to implement registers more recently.
In particular, bits [19:18] are only present with FEAT_RME,
and bits [17:12] will only be present with FEAT_ECV.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-5-peter.maydell@linaro.org
Commit: dcdad2624b445f9ce1a3fdca6a0831d7a7abddd8
https://github.com/qemu/qemu/commit/dcdad2624b445f9ce1a3fdca6a0831d7a7abddd8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M target/arm/cpu-features.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement new FEAT_ECV trap bits
The functionality defined by ID_AA64MMFR0_EL1.ECV == 1 is:
* four new trap bits for various counter and timer registers
* the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control
scaling of the event stream. This is a no-op for us, because we don't
implement the event stream (our WFE is a NOP): all we need to do is
allow CNTHCTL_EL2.ENVTIS to be read and written.
* extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and
TRFCR_EL2.TS: these are all no-ops for us, because we don't implement
FEAT_SPE or FEAT_TRF.
* new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are
"self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning
that no barriers are needed around their accesses. For us these
are just the same as the normal views, because all our sysregs are
inherently self-sychronizing.
In this commit we implement the trap handling and permit the new
CNTHCTL_EL2 bits to be written.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org
Commit: 485eb324e352a53bdf99f90511bd546eebab68f5
https://github.com/qemu/qemu/commit/485eb324e352a53bdf99f90511bd546eebab68f5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are
defined, which are "self-synchronized" views of the physical and
virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers
(meaning that no barriers are needed around accesses to them to
ensure that reads of them do not occur speculatively and out-of-order
with other instructions).
For QEMU, all our system registers are self-synchronized, so we can
simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0
to the new register encodings.
This means we now implement all the functionality required for
ID_AA64MMFR0_EL1.ECV == 0b0001.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-7-peter.maydell@linaro.org
Commit: 2808d3b38a5232e263338e1b812bb1f6c2d56bcf
https://github.com/qemu/qemu/commit/2808d3b38a5232e263338e1b812bb1f6c2d56bcf
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/trace-events
Log Message:
-----------
target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is
implemented. This is similar to the existing CNTVOFF_EL2, except
that it controls a hypervisor-adjustable offset made to the physical
counter and timer.
Implement the handling for this register, which includes control/trap
bits in SCR_EL3 and CNTHCTL_EL2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
Commit: c10a9a517a4518a2b886d5796f90aa1c7a0530f6
https://github.com/qemu/qemu/commit/c10a9a517a4518a2b886d5796f90aa1c7a0530f6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_ECV for 'max' CPU
Enable all FEAT_ECV features on the 'max' CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301183219.2424889-9-peter.maydell@linaro.org
Commit: 1cdcfb6e936c25ef470e886ffe86dd46ef36f0f5
https://github.com/qemu/qemu/commit/1cdcfb6e936c25ef470e886ffe86dd46ef36f0f5
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M MAINTAINERS
M docs/system/arm/b-l475e-iot01a.rst
M hw/gpio/Kconfig
M hw/gpio/meson.build
A hw/gpio/stm32l4x5_gpio.c
M hw/gpio/trace-events
A include/hw/gpio/stm32l4x5_gpio.h
Log Message:
-----------
hw/gpio: Implement STM32L4x5 GPIO
Features supported :
- the 8 STM32L4x5 GPIOs are initialized with their reset values
(except IDR, see below)
- input mode : setting a pin in input mode "externally" (using input
irqs) results in an out irq (transmitted to SYSCFG)
- output mode : setting a bit in ODR sets the corresponding out irq
(if this line is configured in output mode)
- pull-up, pull-down
- push-pull, open-drain
Difference with the real GPIOs :
- Alternate Function and Analog mode aren't implemented :
pins in AF/Analog behave like pins in input mode
- floating pins stay at their last value
- register IDR reset values differ from the real one :
values are coherent with the other registers reset values
and the fact that AF/Analog modes aren't implemented
- setting I/O output speed isn't supported
- locking port bits isn't supported
- ADC function isn't supported
- GPIOH has 16 pins instead of 2 pins
- writing to registers LCKR, AFRL, AFRH and ASCR is ineffective
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1c38129de8a7f3d62ad2800758d9b2ddfccbdca9
https://github.com/qemu/qemu/commit/1c38129de8a7f3d62ad2800758d9b2ddfccbdca9
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M hw/arm/Kconfig
M hw/arm/stm32l4x5_soc.c
M hw/misc/stm32l4x5_syscfg.c
M include/hw/arm/stm32l4x5_soc.h
M include/hw/gpio/stm32l4x5_gpio.h
M include/hw/misc/stm32l4x5_syscfg.h
Log Message:
-----------
hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ddcc4b4b5250f800d500ef1217b28c39812bac2a
https://github.com/qemu/qemu/commit/ddcc4b4b5250f800d500ef1217b28c39812bac2a
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/stm32l4x5_gpio-test.c
Log Message:
-----------
tests/qtest: Add STM32L4x5 GPIO QTest testcase
The testcase contains :
- `test_idr_reset_value()` :
Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR.
- `test_gpio_output_mode()` :
Checks that writing a bit in register ODR results in the corresponding
pin rising or lowering, if this pin is configured in output mode.
- `test_gpio_input_mode()` :
Checks that a input pin set high or low externally results
in the pin rising and lowering.
- `test_pull_up_pull_down()` :
Checks that a floating pin in pull-up/down mode is actually high/down.
- `test_push_pull()` :
Checks that a pin set externally is disconnected when configured in
push-pull output mode, and can't be set externally while in this mode.
- `test_open_drain()` :
Checks that a pin set externally high is disconnected when configured
in open-drain output mode, and can't be set high while in this mode.
- `test_bsrr_brr()` :
Checks that writing to BSRR and BRR has the desired result in ODR.
- `test_clock_enable()` :
Checks that GPIO clock is at the right frequency after enabling it.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240305210444.310665-4-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d572bcb222010b38b382871a23b2f38e2c3f4d2d
https://github.com/qemu/qemu/commit/d572bcb222010b38b382871a23b2f38e2c3f4d2d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M target/arm/tcg/sme_helper.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/sme-smopa-1.c
A tests/tcg/aarch64/sme-smopa-2.c
Log Message:
-----------
target/arm: Fix 32-bit SMOPA
While the 8-bit input elements are sequential in the input vector,
the 32-bit output elements are not sequential in the output matrix.
Do not attempt to compute 2 32-bit outputs at the same time.
Cc: qemu-stable@nongnu.org
Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240305163931.242795-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fd7f95f23d6fe485332c1d4b489eb719fcb7c225
https://github.com/qemu/qemu/commit/fd7f95f23d6fe485332c1d4b489eb719fcb7c225
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-07 (Thu, 07 Mar 2024)
Changed paths:
M hw/rtc/sun4v-rtc.c
M include/hw/rtc/sun4v-rtc.h
Log Message:
-----------
hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016
was unfortunately added with a license of GPL-v3-or-later, which is
not compatible with other QEMU code which has a GPL-v2-only license.
Relicense the code in the .c and the .h file to GPL-v2-or-later,
to make it compatible with the rest of QEMU.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini (for Red Hat) <pbonzini@redhat.com>
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20240223161300.938542-1-peter.maydell@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bbf6c6dbead82292a20951eb1204442a6b838de9
https://github.com/qemu/qemu/commit/bbf6c6dbead82292a20951eb1204442a6b838de9
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-03-08 (Fri, 08 Mar 2024)
Changed paths:
M target/arm/meson.build
A target/arm/tcg/cpu-v7m.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/meson.build
Log Message:
-----------
target/arm: Move v7m-related code from cpu32.c into a separate file
Move the code to a separate file so that we do not have to compile
it anymore if CONFIG_ARM_V7M is not set.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-id: 20240308141051.536599-2-thuth@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a146c6f88c169f054284f16ad8dcd565892d3db8
https://github.com/qemu/qemu/commit/a146c6f88c169f054284f16ad8dcd565892d3db8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-08 (Fri, 08 Mar 2024)
Changed paths:
M MAINTAINERS
M docs/system/arm/b-l475e-iot01a.rst
M docs/system/arm/emulation.rst
M hw/arm/Kconfig
M hw/arm/stm32l4x5_soc.c
M hw/gpio/Kconfig
M hw/gpio/meson.build
A hw/gpio/stm32l4x5_gpio.c
M hw/gpio/trace-events
M hw/misc/stm32l4x5_syscfg.c
M hw/rtc/sun4v-rtc.c
M include/hw/arm/stm32l4x5_soc.h
A include/hw/gpio/stm32l4x5_gpio.h
M include/hw/misc/stm32l4x5_syscfg.h
M include/hw/rtc/sun4v-rtc.h
M target/arm/cpu-features.h
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/meson.build
A target/arm/tcg/cpu-v7m.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
M target/arm/tcg/meson.build
M target/arm/tcg/sme_helper.c
M target/arm/trace-events
M tests/qtest/meson.build
A tests/qtest/stm32l4x5_gpio-test.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/sme-smopa-1.c
A tests/tcg/aarch64/sme-smopa-2.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240308' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Implement FEAT_ECV
* STM32L4x5: Implement GPIO device
* Fix 32-bit SMOPA
* Refactor v7m related code from cpu32.c into its own file
* hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 08 Mar 2024 15:49:49 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240308' of
https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Move v7m-related code from cpu32.c into a separate file
hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
target/arm: Fix 32-bit SMOPA
tests/qtest: Add STM32L4x5 GPIO QTest testcase
hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
hw/gpio: Implement STM32L4x5 GPIO
target/arm: Enable FEAT_ECV for 'max' CPU
target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
target/arm: Implement new FEAT_ECV trap bits
target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
target/arm: use FIELD macro for CNTHCTL bit definitions
target/arm: Timer _EL02 registers UNDEF for E2H == 0
target/arm: Move some register related defines to internals.h
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 84644ac1b0f80d41b8a2f66547b83b2ad4a98576
https://github.com/qemu/qemu/commit/84644ac1b0f80d41b8a2f66547b83b2ad4a98576
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-08 (Fri, 08 Mar 2024)
Changed paths:
M qapi/ui.json
M ui/cocoa.m
Log Message:
-----------
Merge tag 'darwin-20240305' of https://github.com/philmd/qemu into staging
Darwin Cocoa patches:
- Add 'zoom-interpolation' to smooth scaled display with 'zoom-to-fit' (Carwyn)
- Set clipsToBounds on macOS 14 to fix window clipping (David)
- Use NSWindow's ability to resize (Akihiko)
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# gpg: Signature made Tue 05 Mar 2024 11:05:11 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'darwin-20240305' of https://github.com/philmd/qemu:
ui/cocoa: Remove stretch_video flag
ui/cocoa: Call console_select() with the BQL
ui/cocoa: Make window resizable
ui/cocoa: Remove normalWindow
ui/cocoa: Let the platform toggle fullscreen
ui/cocoa: Fix pause label coordinates
ui/cocoa: Scale with NSView instead of Core Graphics
ui/cocoa: Release specific mouse buttons
ui/cocoa: Immediately call [-QemuCocoaView handleMouseEvent:buttons:]
ui/cocoa: Split [-QemuCocoaView handleEventLocked:]
ui/cocoa: Fix window clipping on macOS 14
ui/cocoa: add zoom-interpolation display option
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/b507dec3f385...84644ac1b0f8
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