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[Qemu-commits] [qemu/qemu] b19bbf: target/riscv: Remove redundant insn l
From: |
Richard Henderson |
Subject: |
[Qemu-commits] [qemu/qemu] b19bbf: target/riscv: Remove redundant insn length check f... |
Date: |
Tue, 06 Aug 2024 02:43:08 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: b19bbf2cf11297e8c8efd5a048b9e533d8fdface
https://github.com/qemu/qemu/commit/b19bbf2cf11297e8c8efd5a048b9e533d8fdface
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-08-06 (Tue, 06 Aug 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
Log Message:
-----------
target/riscv: Remove redundant insn length check for zama16b
Compressed encodings also applies to zama16b.
https://github.com/riscv/riscv-isa-manual/pull/1557
Suggested-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240802072417.659-2-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 30d24145da72dc3f64d9d720ac2befad28e1daa2
https://github.com/qemu/qemu/commit/30d24145da72dc3f64d9d720ac2befad28e1daa2
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-08-06 (Tue, 06 Aug 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvd.c.inc
Log Message:
-----------
target/riscv: Add MXLEN check for F/D/Q applies to zama16b
Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q
extensions.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240802072417.659-3-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5e54b439f5be1e604453d9b02d85685a266121da
https://github.com/qemu/qemu/commit/5e54b439f5be1e604453d9b02d85685a266121da
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-08-06 (Tue, 06 Aug 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvd.c.inc
Log Message:
-----------
target/riscv: Relax fld alignment requirement
According to the risc-v specification:
"FLD and FSD are only guaranteed to execute atomically if the effective
address is naturally aligned and XLEN≥64."
We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does
not violate the rules. But it will hide some problems. So relax it to
MO_ATOM_NONE.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240802072417.659-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 73b0195416c4063c7cbf22b305ee6c48d6cd2d24
https://github.com/qemu/qemu/commit/73b0195416c4063c7cbf22b305ee6c48d6cd2d24
Author: Atish Patra <atishp@rivosinc.com>
Date: 2024-08-06 (Tue, 06 Aug 2024)
Changed paths:
M target/riscv/pmu.c
Log Message:
-----------
target/riscv: Add asserts for out-of-bound access
Coverity complained about the possible out-of-bounds access with
counter_virt/counter_virt_prev because these two arrays are
accessed with privilege mode. However, these two arrays are accessed
only when virt is enabled. Thus, the privilege mode can't be M mode.
Add the asserts anyways to detect any wrong usage of these arrays
in the future.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Fixes: Coverity CID 1558459
Fixes: Coverity CID 1558462
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240724-fixes-v1-1-4a64596b0d64@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b3a34eb90d8264bd73ccb25295b1a7e271a9029c
https://github.com/qemu/qemu/commit/b3a34eb90d8264bd73ccb25295b1a7e271a9029c
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-08-06 (Tue, 06 Aug 2024)
Changed paths:
M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
M roms/opensbi
Log Message:
-----------
roms/opensbi: Update to v1.5.1
A new minor version of OpenSBI was just released after our bump to
OpenSBI 1.5. It contains significant bug fixes that it's worth doing
a new update for QEMU 9.1.
Submodule roms/opensbi 455de672dd..43cace6c36:
> lib: sbi: check result of pmp_get() in is_pmp_entry_mapped()
> lib: sbi: fwft: fix incorrect size passed to sbi_zalloc()
> lib: sbi: dbtr: fix potential NULL pointer dereferences
> include: Adjust Sscofpmf mhpmevent mask for upper 8 bits
> lib: sbi_hsm: Save/restore menvcfg only when it exists
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240805120259.1705016-2-dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c659b7b3b4925f8cef486a3ee64e911519495782
https://github.com/qemu/qemu/commit/c659b7b3b4925f8cef486a3ee64e911519495782
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-08-06 (Tue, 06 Aug 2024)
Changed paths:
M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
M roms/opensbi
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/pmu.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20240806-2' of
https://github.com/alistair23/qemu into staging
RISC-V PR for 9.1
* roms/opensbi: update to v1.5.1
* target/riscv: Add asserts for out-of-bound access
* Remove redundant insn length check for zama16b
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# gpg: Signature made Tue 06 Aug 2024 04:22:52 PM AEST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20240806-2' of https://github.com/alistair23/qemu:
roms/opensbi: Update to v1.5.1
target/riscv: Add asserts for out-of-bound access
target/riscv: Relax fld alignment requirement
target/riscv: Add MXLEN check for F/D/Q applies to zama16b
target/riscv: Remove redundant insn length check for zama16b
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/e7207a9971dd...c659b7b3b492
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