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[Qemu-commits] [qemu/qemu] ff99f9: target/riscv: Add a property to set v
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] ff99f9: target/riscv: Add a property to set vl to ceil(AVL/2) |
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Date: |
Fri, 13 Sep 2024 02:32:14 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: ff99f9fadf9aaa168d04259dbcea32b930177531
https://github.com/qemu/qemu/commit/ff99f9fadf9aaa168d04259dbcea32b930177531
Author: Jason Chien <jason.chien@sifive.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Add a property to set vl to ceil(AVL/2)
RVV spec allows implementations to set vl with values within
[ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a
property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). This
behavior helps identify compiler issues and bugs.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20240722175004.23666-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 95919ac3d10519bfbc23178cdbfc771cb53a8e6e
https://github.com/qemu/qemu/commit/95919ac3d10519bfbc23178cdbfc771cb53a8e6e
Author: Haibo Xu <haibo1.xu@intel.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A tests/data/acpi/riscv64/virt/SRAT.numamem
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: Add empty ACPI SRAT data file for RISC-V
As per process documented (steps 1-3) in bios-tables-test.c, add
empty AML data file for RISC-V ACPI SRAT table and add the entry
in bios-tables-test-allowed-diff.h.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID:
<0e30216273f2f59916bc651350578d8e8bc3a75f.1723172696.git.haibo1.xu@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 45121ff0b7a312a6ee8ad0383196a7fe77f8fe2f
https://github.com/qemu/qemu/commit/45121ff0b7a312a6ee8ad0383196a7fe77f8fe2f
Author: Haibo Xu <haibo1.xu@intel.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V
Add ACPI SRAT table test case for RISC-V when NUMA was enabled.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID:
<a6f7e1a4b20ff7eb199e94ca0c8aa2e6794ce5b2.1723172696.git.haibo1.xu@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bfe975726dec4599551b7701ceb8ce690e9d0cd5
https://github.com/qemu/qemu/commit/bfe975726dec4599551b7701ceb8ce690e9d0cd5
Author: Haibo Xu <haibo1.xu@intel.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M tests/data/acpi/riscv64/virt/SRAT.numamem
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: Add expected ACPI SRAT AML file for RISC-V
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI SRAT AML data file for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.
This is a new file being added for the first time. Hence, iASL diff
output is not added.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID:
<a667480203b35508038176c8ce4722370294cc57.1723172696.git.haibo1.xu@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d84e87613ff8328c6745cc82919053ed420850aa
https://github.com/qemu/qemu/commit/d84e87613ff8328c6745cc82919053ed420850aa
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule
Gitlab issue [1] reports a misleading error when trying to run a 'rv64'
cpu with 'zfinx' and without 'f':
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
qemu-system-riscv64: Zfinx cannot be supported together with F extension
The user explicitly disabled F and the error message mentions a conflict
with Zfinx and F.
The problem isn't the error reporting, but the logic used when applying
the implied ZFA rule that enables RVF unconditionally, without honoring
user choice (i.e. keep F disabled).
Change cpu_enable_implied_rule() to check if the user deliberately
disabled a MISA bit. In this case we shouldn't either re-enable the bit
nor apply any implied rules related to it.
After this change the error message now shows:
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
qemu-system-riscv64: Zfa extension requires F extension
Disabling 'zfa':
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu
rv64,zfinx=true,f=false,zfa=false
qemu-system-riscv64: D extension requires F extension
And finally after disabling 'd':
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu
rv64,zfinx=true,f=false,zfa=false,d=false
(OpenSBI boots ...)
[1] https://gitlab.com/qemu-project/qemu/-/issues/2486
Cc: Frank Chang <frank.chang@sifive.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2486
Fixes: 047da861f9 ("target/riscv: Introduce extension implied rule helpers")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240824173338.316666-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d64109f00651e81396a4111878c3744962c800a2
https://github.com/qemu/qemu/commit/d64109f00651e81396a4111878c3744962c800a2
Author: Vladimir Isaev <vladimir.isaev@syntacore.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: fix za64rs enabling
za64rs requires priv 1.12 when enabled by priv 1.11.
This fixes annoying warning:
warning: disabling za64rs extension for hart 0x00000000 because privilege spec
version does not match
on priv 1.11 CPUs.
Fixes: 68c9e54beae8 ("target/riscv: do not enable all named features by
default")
Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240823063431.17474-1-vladimir.isaev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 11c0defde17cff32d665612f5894f0ba6e6db567
https://github.com/qemu/qemu/commit/11c0defde17cff32d665612f5894f0ba6e6db567
Author: Alistair Francis <alistair23@gmail.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target: riscv: Enable Bit Manip for OpenTitan Ibex CPU
The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc
and Zbs bit-manipulation sub-extensions ratified in
v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable
them in QEMU as well.
1: https://github.com/lowRISC/opentitan/pull/9748
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240823003231.3522113-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fb12bd1cab21897d1ae0883da1a86a88f43fec88
https://github.com/qemu/qemu/commit/fb12bd1cab21897d1ae0883da1a86a88f43fec88
Author: Andrew Jones <ajones@ventanamicro.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: Fix the group bit setting of AIA
Just as the hart bit setting of the AIA should be calculated as
ceil(log2(max_hart_id + 1)) the group bit setting should be
calculated as ceil(log2(max_group_id + 1)). The hart bits are
implemented by passing max_hart_id to find_last_bit() and adding
one to the result. Do the same for the group bit setting.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240821075040.498945-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 34130df267e12c864bc0eb55b997665b3349cc86
https://github.com/qemu/qemu/commit/34130df267e12c864bc0eb55b997665b3349cc86
Author: Andrew Jones <ajones@ventanamicro.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/time_helper.c
Log Message:
-----------
target/riscv: Stop timer with infinite timecmp
While the spec doesn't state it, setting timecmp to UINT64_MAX is
another way to stop a timer, as it's considered setting the next
timer event to occur at infinity. And, even if the time CSR does
eventually reach UINT64_MAX, the very next tick will bring it back to
zero, once again less than timecmp. For this reason
riscv_timer_write_timecmp() special cases UINT64_MAX. However, if a
previously set timecmp has not yet expired, then setting timecmp to
UINT64_MAX to disable / stop it would not work, as the special case
left the previous QEMU timer active, which would then still deliver
an interrupt at that previous timecmp time. Ensure the stopped timer
will not still deliver an interrupt by also deleting the QEMU timer
in the UINT64_MAX special case.
Fixes: ae0edf2188b3 ("target/riscv: No need to re-start QEMU timer when timecmp
== UINT64_MAX")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240829084002.1805006-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: deaf90d6283e2bb6ef44f8ec5748ab8d2be1a447
https://github.com/qemu/qemu/commit/deaf90d6283e2bb6ef44f8ec5748ab8d2be1a447
Author: Maria Klauchek <m.klauchek@syntacore.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension
FCSR is a part of F extension. Print it to log if FPU option is enabled.
Signed-off-by: Maria Klauchek <m.klauchek@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240902103433.18424-1-m.klauchek@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fb43fa7085cbded1ebeb9bc8c7e107ef53457e99
https://github.com/qemu/qemu/commit/fb43fa7085cbded1ebeb9bc8c7e107ef53457e99
Author: Milan P. Stanić <mps@arvanta.net>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M util/cpuinfo-riscv.c
Log Message:
-----------
util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc
build fails on musl libc (alpine linux) with this error:
../util/cpuinfo-riscv.c: In function 'cpuinfo_init':
../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe' undeclared (first
use in this function); did you mean 'riscv_hwprobe'?
63 | if (syscall(__NR_riscv_hwprobe, &pair, 1, 0, NULL, 0) == 0
| ^~~~~~~~~~~~~~~~~~
| riscv_hwprobe
../util/cpuinfo-riscv.c:63:21: note: each undeclared identifier is reported
only once for each function it appears in
ninja: subcommand failed
add '#include "asm/unistd.h"' to util/cpuinfo-riscv.c fixes build
Signed-off-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240905150702.2484-1-mps@arvanta.net>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5ed2a2f8c80051b9a31f57e713834215e6ddd95e
https://github.com/qemu/qemu/commit/5ed2a2f8c80051b9a31f57e713834215e6ddd95e
Author: Alvin Chang <alvinga@andestech.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/debug.c
Log Message:
-----------
target/riscv: Preliminary textra trigger CSR writting support
This commit allows program to write textra trigger CSR for type 2, 3, 6
triggers. In this preliminary patch, the textra.MHVALUE and the
textra.MHSELECT fields are allowed to be configured. Other fields, such
as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to
zero for now.
For textra.MHSELECT field, the only legal values are 0 (ignore) and 4
(mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and
writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is
aligned to RISC-V SPIKE simulator.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240826024657.262553-2-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a664b31d507775eb59fb0af42a412e1e7f47680a
https://github.com/qemu/qemu/commit/a664b31d507775eb59fb0af42a412e1e7f47680a
Author: Alvin Chang <alvinga@andestech.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/debug.c
M target/riscv/debug.h
Log Message:
-----------
target/riscv: Add textra matching condition for the triggers
According to RISC-V Debug specification, the optional textra32 and
textra64 trigger CSRs can be used to configure additional matching
conditions for the triggers. For example, if the textra.MHSELECT field
is set to 4 (mcontext), this trigger will only match or fire if the low
bits of mcontext/hcontext equal textra.MHVALUE field.
This commit adds the aforementioned matching condition as common trigger
matching conditions. Currently, the only legal values of textra.MHSELECT
are 0 (ignore) and 4 (mcontext). When textra.MHSELECT is 0, we pass the
checking. When textra.MHSELECT is 4, we compare textra.MHVALUE with
mcontext CSR. The remaining fields, such as textra.SBYTEMASK,
textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus,
we skip checking them here.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240826024657.262553-3-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 407efed34f28ac4df38b32dc233c5d6365bf0995
https://github.com/qemu/qemu/commit/407efed34f28ac4df38b32dc233c5d6365bf0995
Author: Tomasz Jeznach <tjeznach@rivosinc.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M include/exec/memattrs.h
Log Message:
-----------
exec/memtxattr: add process identifier to the transaction attributes
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240903201633.93182-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d8acb0a48061d152043b105439a23f59f65c9184
https://github.com/qemu/qemu/commit/d8acb0a48061d152043b105439a23f59f65c9184
Author: Tomasz Jeznach <tjeznach@rivosinc.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A hw/riscv/riscv-iommu-bits.h
Log Message:
-----------
hw/riscv: add riscv-iommu-bits.h
This header will be used by the RISC-V IOMMU emulation to be added
in the next patch. Due to its size it's being sent in separate for
an easier review.
One thing to notice is that this header can be replaced by the future
Linux RISC-V IOMMU driver header, which would become a linux-header we
would import instead of keeping our own. The Linux implementation isn't
upstream yet so for now we'll have to manage riscv-iommu-bits.h.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c3fa3f648c846962c3b0408cc3e314dd989b7e48
https://github.com/qemu/qemu/commit/c3fa3f648c846962c3b0408cc3e314dd989b7e48
Author: Tomasz Jeznach <tjeznach@rivosinc.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/meson.build
M hw/riscv/riscv-iommu-bits.h
A hw/riscv/riscv-iommu.c
A hw/riscv/riscv-iommu.h
A hw/riscv/trace-events
A hw/riscv/trace.h
A include/hw/riscv/iommu.h
M meson.build
Log Message:
-----------
hw/riscv: add RISC-V IOMMU base emulation
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
Add the foundation of the device emulation for RISC-V IOMMU. It includes
support for s-stage (sv32, sv39, sv48, sv57 caps) and g-stage (sv32x4,
sv39x4, sv48x4, sv57x4 caps).
Other capabilities like ATS and DBG support will be added incrementally
in the next patches.
Co-developed-by: Sebastien Boeuf <seb@rivosinc.com>
Signed-off-by: Sebastien Boeuf <seb@rivosinc.com>
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f6f99908bd93a6f9f335ba23e01c90c9b9715909
https://github.com/qemu/qemu/commit/f6f99908bd93a6f9f335ba23e01c90c9b9715909
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M docs/specs/pci-ids.rst
M include/hw/pci/pci.h
Log Message:
-----------
pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
The RISC-V IOMMU PCI device we're going to add next is a reference
implementation of the riscv-iommu spec [1], which predicts that the
IOMMU can be implemented as a PCIe device.
However, RISC-V International (RVI), the entity that ratified the
riscv-iommu spec, didn't bother assigning a PCI ID for this IOMMU PCIe
implementation that the spec predicts. This puts us in an uncommon
situation because we want to add the reference IOMMU PCIe implementation
but we don't have a PCI ID for it.
Given that RVI doesn't provide a PCI ID for it we reached out to Red Hat
and Gerd Hoffman, and they were kind enough to give us a PCI ID for the
RISC-V IOMMU PCI reference device.
Thanks Red Hat and Gerd for this RISC-V IOMMU PCIe device ID.
[1] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Message-ID: <20240903201633.93182-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8d8c34c877fb62d05ae737eb8cf4a616d1476e8b
https://github.com/qemu/qemu/commit/8d8c34c877fb62d05ae737eb8cf4a616d1476e8b
Author: Tomasz Jeznach <tjeznach@rivosinc.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M hw/riscv/meson.build
A hw/riscv/riscv-iommu-pci.c
Log Message:
-----------
hw/riscv: add riscv-iommu-pci reference device
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2911aa44bd1691693324d49483f6b774edb68bfd
https://github.com/qemu/qemu/commit/2911aa44bd1691693324d49483f6b774edb68bfd
Author: Tomasz Jeznach <tjeznach@rivosinc.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a8954ce2a3244730ad14bc1f3d72607bd95c8a21
https://github.com/qemu/qemu/commit/a8954ce2a3244730ad14bc1f3d72607bd95c8a21
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M tests/qtest/libqos/meson.build
A tests/qtest/libqos/riscv-iommu.c
A tests/qtest/libqos/riscv-iommu.h
M tests/qtest/meson.build
A tests/qtest/riscv-iommu-test.c
Log Message:
-----------
test/qtest: add riscv-iommu-pci tests
To test the RISC-V IOMMU emulation we'll use its PCI representation.
Create a new 'riscv-iommu-pci' libqos device that will be present with
CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this
device will only be consumed by the RISC-V libqos machine.
Start with basic tests: a PCI sanity check and a reset state register
test. The reset test was taken from the RISC-V IOMMU spec chapter 5.2,
"Reset behavior".
More tests will be added later.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e2b3ca847dc95ee686ffbc544979724a34e514f4
https://github.com/qemu/qemu/commit/e2b3ca847dc95ee686ffbc544979724a34e514f4
Author: Tomasz Jeznach <tjeznach@rivosinc.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M hw/riscv/riscv-iommu.c
M hw/riscv/riscv-iommu.h
Log Message:
-----------
hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
to hold entries from the DDT. This includes implementation for all cache
commands that are marked as 'not implemented'.
There are some artifacts included in the cache that predicts s-stage and
g-stage elements, although we don't support it yet. We'll introduce them
next.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 38467fdfa1e468b173df55b131d888b99a7ad510
https://github.com/qemu/qemu/commit/38467fdfa1e468b173df55b131d888b99a7ad510
Author: Tomasz Jeznach <tjeznach@rivosinc.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M hw/riscv/riscv-iommu-bits.h
M hw/riscv/riscv-iommu.c
M hw/riscv/riscv-iommu.h
M hw/riscv/trace-events
Log Message:
-----------
hw/riscv/riscv-iommu: add ATS support
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 548a38851528086a7520aa4482a426d813354941
https://github.com/qemu/qemu/commit/548a38851528086a7520aa4482a426d813354941
Author: Tomasz Jeznach <tjeznach@rivosinc.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M hw/riscv/riscv-iommu-bits.h
M hw/riscv/riscv-iommu.c
Log Message:
-----------
hw/riscv/riscv-iommu: add DBG support
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 62b62b05d8e219b5bffe56b3cd8930b1897b3b95
https://github.com/qemu/qemu/commit/62b62b05d8e219b5bffe56b3cd8930b1897b3b95
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M tests/qtest/libqos/riscv-iommu.h
M tests/qtest/riscv-iommu-test.c
Log Message:
-----------
qtest/riscv-iommu-test: add init queues test
Add an additional test to further exercise the IOMMU where we attempt to
initialize the command, fault and page-request queues.
These steps are taken from chapter 6.2 of the RISC-V IOMMU spec,
"Guidelines for initialization". It emulates what we expect from the
software/OS when initializing the IOMMU.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1405a6dc5e625346d3628f1756eb73e30c15402e
https://github.com/qemu/qemu/commit/1405a6dc5e625346d3628f1756eb73e30c15402e
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M docs/specs/index.rst
A docs/specs/riscv-iommu.rst
M docs/system/riscv/virt.rst
Log Message:
-----------
docs/specs: add riscv-iommu
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 55bf3f42757707bce26c3f5dcd52890fa209f110
https://github.com/qemu/qemu/commit/55bf3f42757707bce26c3f5dcd52890fa209f110
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target_arch_cpu.h
Log Message:
-----------
bsd-user: Implement RISC-V CPU initialization and main loop
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-2-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cf7024b98d02e239c4fab08c621a9e4606de463f
https://github.com/qemu/qemu/commit/cf7024b98d02e239c4fab08c621a9e4606de463f
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M bsd-user/riscv/target_arch_cpu.h
Log Message:
-----------
bsd-user: Add RISC-V CPU execution loop and syscall handling
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-3-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fb0ac3a2263c9b0a51083013f62d7e286e3636e8
https://github.com/qemu/qemu/commit/fb0ac3a2263c9b0a51083013f62d7e286e3636e8
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M bsd-user/riscv/target_arch_cpu.h
Log Message:
-----------
bsd-user: Implement RISC-V CPU register cloning and reset functions
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-4-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d869a788e2801a405d66d5be567b504f2cf397e2
https://github.com/qemu/qemu/commit/d869a788e2801a405d66d5be567b504f2cf397e2
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target_arch.h
A bsd-user/riscv/target_arch_cpu.c
Log Message:
-----------
bsd-user: Implement RISC-V TLS register setup
Included the prototype for the 'target_cpu_set_tls' function in the
'target_arch.h' header file. This function is responsible for setting
the Thread Local Storage (TLS) register for RISC-V architecture.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-5-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cb018c4907b84693c1545b5cbfdf8311cea5b6e8
https://github.com/qemu/qemu/commit/cb018c4907b84693c1545b5cbfdf8311cea5b6e8
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target_arch_elf.h
Log Message:
-----------
bsd-user: Add RISC-V ELF definitions and hardware capability detection
Introduced RISC-V specific ELF definitions and hardware capability
detection.
Additionally, a function to retrieve hardware capabilities
('get_elf_hwcap') is implemented, which returns the common bits set in
each CPU's ISA strings.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-6-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0e4c056709a7e747cad360d4702f287ef476e88a
https://github.com/qemu/qemu/commit/0e4c056709a7e747cad360d4702f287ef476e88a
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target_arch_reg.h
Log Message:
-----------
bsd-user: Define RISC-V register structures and register copying
Added definitions for RISC-V register structures, including
general-purpose registers and floating-point registers, in
'target_arch_reg.h'. Implemented the 'target_copy_regs' function to
copy register values from the CPU state to the target register
structure, ensuring proper endianness handling using 'tswapreg'.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-7-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fe1a41dadb26637189dae4c5fe62cf664884cbc8
https://github.com/qemu/qemu/commit/fe1a41dadb26637189dae4c5fe62cf664884cbc8
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target_arch_sigtramp.h
Log Message:
-----------
bsd-user: Add RISC-V signal trampoline setup function
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-8-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7b4e8a8b2ab07829d13e57542605740814de349f
https://github.com/qemu/qemu/commit/7b4e8a8b2ab07829d13e57542605740814de349f
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target_arch_sysarch.h
Log Message:
-----------
bsd-user: Implement RISC-V sysarch system call emulation
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch'
system call for the RISC-V architecture.
Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that
the operation is not supported.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-9-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1d7000e2a7295a00741953d5815e5bb0a262404c
https://github.com/qemu/qemu/commit/1d7000e2a7295a00741953d5815e5bb0a262404c
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target_arch_thread.h
Log Message:
-----------
bsd-user: Add RISC-V thread setup and initialization support
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers based on
the provided image information.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-10-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4af09227409924a8ec9996b708fee7487c94eaa1
https://github.com/qemu/qemu/commit/4af09227409924a8ec9996b708fee7487c94eaa1
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target_arch_vmparam.h
Log Message:
-----------
bsd-user: Define RISC-V VM parameters and helper functions
Added definitions for RISC-V VM parameters, including maximum and
default sizes for text, data, and stack, as well as address space
limits.
Implemented helper functions for retrieving and setting specific
values in the CPU state, such as stack pointer and return values.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-11-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 998369de5389e3f65bfeee31b91d306d815d4f09
https://github.com/qemu/qemu/commit/998369de5389e3f65bfeee31b91d306d815d4f09
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target_syscall.h
Log Message:
-----------
bsd-user: Define RISC-V system call structures and constants
Introduced definitions for the RISC-V system call interface, including
the 'target_pt_regs' structure that outlines the register storage
layout during a system call.
Added constants for hardware machine identifiers.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-12-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 430ad2909fdee7310681d7fa895ec757e5fc1b03
https://github.com/qemu/qemu/commit/430ad2909fdee7310681d7fa895ec757e5fc1b03
Author: Warner Losh <imp@bsdimp.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target.h
Log Message:
-----------
bsd-user: Add generic RISC-V64 target definitions
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-13-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8533d8176054f15cadca54ce9b58e5d9d6d047e0
https://github.com/qemu/qemu/commit/8533d8176054f15cadca54ce9b58e5d9d6d047e0
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/target_arch_signal.h
Log Message:
-----------
bsd-user: Define RISC-V signal handling structures and constants
Added definitions for RISC-V signal handling, including structures
and constants for managing signal frames and context
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-14-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 33044294e84435299ff038900eecc3bff116d67e
https://github.com/qemu/qemu/commit/33044294e84435299ff038900eecc3bff116d67e
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A bsd-user/riscv/signal.c
Log Message:
-----------
bsd-user: Implement RISC-V signal trampoline setup functions
Added functions for setting up the RISC-V signal trampoline and signal
frame:
'set_sigtramp_args()': Configures the RISC-V CPU state with arguments
for the signal handler. It sets up the registers with the signal
number,pointers to the signal info and user context, the signal handler
address, and the signal frame pointer.
'setup_sigframe_arch()': Initializes the signal frame with the current
machine context.This function copies the context from the CPU state to
the signal frame, preparing it for the signal handler.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-15-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4c6e6686984411ada9a95bd977489a2e79e6854a
https://github.com/qemu/qemu/commit/4c6e6686984411ada9a95bd977489a2e79e6854a
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M bsd-user/riscv/signal.c
Log Message:
-----------
bsd-user: Implement 'get_mcontext' for RISC-V
Added the 'get_mcontext' function to extract and populate
the RISC-V machine context from the CPU state.
This function is used to gather the current state of the
general-purpose registers and store it in a 'target_mcontext_'
structure.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-16-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4a29b2f43cdbf3a9cf082ae9efe58f39a2dd07a1
https://github.com/qemu/qemu/commit/4a29b2f43cdbf3a9cf082ae9efe58f39a2dd07a1
Author: Mark Corbin <mark@dibsco.co.uk>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M bsd-user/riscv/signal.c
Log Message:
-----------
bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn'
functions for RISC-V architecture,
Both functions ensure that the CPU state and user context are properly
managed.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-17-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b02e827be47610b02c69004ab9ab689d5769e493
https://github.com/qemu/qemu/commit/b02e827be47610b02c69004ab9ab689d5769e493
Author: Warner Losh <imp@bsdimp.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
A configs/targets/riscv64-bsd-user.mak
Log Message:
-----------
bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240907031927.1908-18-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: abc0ad7fe2c068f17ca36eb878a4212ae418b851
https://github.com/qemu/qemu/commit/abc0ad7fe2c068f17ca36eb878a4212ae418b851
Author: Samuel Holland <samuel.holland@sifive.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/shakti_c.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv: Respect firmware ELF entry point
When riscv_load_firmware() loads an ELF, the ELF segment addresses are
used, not the passed-in firmware_load_addr. The machine models assume
the firmware entry point is what they provided for firmware_load_addr,
and use that address to generate the boot ROM, so if the ELF is linked
at any other address, the boot ROM will jump to empty memory.
Pass back the ELF entry point to use when generating the boot ROM, so
the boot ROM can jump to firmware loaded anywhere in RAM. For example,
on the virt machine, this allows using an OpenSBI fw_dynamic.elf built
with FW_TEXT_START values other than 0x80000000.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240817002651.3209701-1-samuel.holland@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8cd23f5af826d799e6cbcfdaf94f5fae5a23df12
https://github.com/qemu/qemu/commit/8cd23f5af826d799e6cbcfdaf94f5fae5a23df12
Author: Alexandre Ghiti <alexghiti@rivosinc.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
Log Message:
-----------
target: riscv: Add Svvptc extension support
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension.
Since qemu already exposes Svvptc behaviour, let's enable it by default
since it allows to drastically reduce the number of sfence.vma emitted
by S-mode.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240828083651.203861-1-alexghiti@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4817893932877351e10ae4944c3423a886f86bc7
https://github.com/qemu/qemu/commit/4817893932877351e10ae4944c3423a886f86bc7
Author: Andrew Jones <ajones@ventanamicro.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv32: Fix masking of physical address
C doesn't extend the sign bit for unsigned types since there isn't a
sign bit to extend. This means a promotion of a u32 to a u64 results
in the upper 32 bits of the u64 being zero. If that result is then
used as a mask on another u64 the upper 32 bits will be cleared. rv32
physical addresses may be up to 34 bits wide, so we don't want to
clear the high bits while page aligning the address. The fix is to
use hwaddr for the mask, which, even on rv32, is 64-bits wide.
Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP
entries.")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240909083241.43836-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4f4d5379382b60306f53da42a6d82c587a2db768
https://github.com/qemu/qemu/commit/4f4d5379382b60306f53da42a6d82c587a2db768
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M target/riscv/Kconfig
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv/cpu_helper: Fix linking problem with semihosting disabled
If QEMU has been configured with "--without-default-devices", the build
is currently failing with:
/usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
in function `riscv_cpu_do_interrupt':
.../qemu/target/riscv/cpu_helper.c:1678:(.text+0x2214): undefined
reference to `do_common_semihosting'
We always want semihosting to be enabled if TCG is available, so change
the "imply" statements in the Kconfig file to "select", and make sure to
avoid calling into do_common_semihosting() if TCG is not available.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240906094858.718105-1-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 90d5d3c1115399d8e27621efd69dfa74a35a4932
https://github.com/qemu/qemu/commit/90d5d3c1115399d8e27621efd69dfa74a35a4932
Author: Tomasz Jeznach <tjeznach@rivosinc.com>
Date: 2024-09-12 (Thu, 12 Sep 2024)
Changed paths:
M hw/intc/riscv_imsic.c
Log Message:
-----------
hw/intc: riscv-imsic: Fix interrupt state updates.
The IMSIC state variable eistate[] is modified by CSR instructions
within a range dedicated to the local CPU and by MMIO writes from any CPU.
Access to eistate from MMIO accessors is protected by the BQL, but
read-modify-write (RMW) sequences from CSRRW do not acquire the BQL,
making the RMW sequence vulnerable to a race condition with MMIO access
from a remote CPU.
This race can manifest as missing IPI or MSI in multi-CPU systems, eg:
[ 43.008092] watchdog: BUG: soft lockup - CPU#2 stuck for 27s!
[kworker/u19:1:52]
[ 43.011723] CPU: 2 UID: 0 PID: 52 Comm: kworker/u19:1 Not tainted 6.11.0-rc6
[ 43.013070] Workqueue: events_unbound deferred_probe_work_func
[ 43.018776] [<ffffffff800b4a86>] smp_call_function_many_cond+0x190/0x5c2
[ 43.019205] [<ffffffff800b4f28>] on_each_cpu_cond_mask+0x20/0x32
[ 43.019447] [<ffffffff8001069a>] __flush_tlb_range+0xf2/0x190
[ 43.019683] [<ffffffff80010914>] flush_tlb_kernel_range+0x20/0x28
The interrupt line raise/lower sequence was changed to prevent a race
between the evaluation of the eistate and the execution of the qemu_irq
raise/lower, ensuring that the interrupt line is not incorrectly
deactivated based on a stale topei check result. To avoid holding BQL
all modifications of eistate are converted to atomic operations.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID:
<a7604e4d61068ca4d384ae2a1377e1521d4d0235.1725651699.git.tjeznach@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1d7fdb15af82e4e07e7e1652f6627d543e56de0d
https://github.com/qemu/qemu/commit/1d7fdb15af82e4e07e7e1652f6627d543e56de0d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M .gitlab-ci.d/crossbuilds.yml
Log Message:
-----------
.gitlab-ci.d/crossbuilds.yml: Force 'make check' single-threaded for
cross-i686-tci
The cross-i686-tci CI job is persistently flaky with various tests
hitting timeouts. One theory for why this is happening is that we're
running too many tests in parallel and so sometimes a test gets
starved of CPU and isn't able to complete within the timeout.
(The environment this CI job runs in seems to cause us to default
to a parallelism of 9 in the main CI.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20240912151003.2045031-1-peter.maydell@linaro.org
Commit: b620c1c6a407b07a5168e47634cc0455301d96db
https://github.com/qemu/qemu/commit/b620c1c6a407b07a5168e47634cc0455301d96db
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
A bsd-user/riscv/signal.c
A bsd-user/riscv/target.h
A bsd-user/riscv/target_arch.h
A bsd-user/riscv/target_arch_cpu.c
A bsd-user/riscv/target_arch_cpu.h
A bsd-user/riscv/target_arch_elf.h
A bsd-user/riscv/target_arch_reg.h
A bsd-user/riscv/target_arch_signal.h
A bsd-user/riscv/target_arch_sigtramp.h
A bsd-user/riscv/target_arch_sysarch.h
A bsd-user/riscv/target_arch_thread.h
A bsd-user/riscv/target_arch_vmparam.h
A bsd-user/riscv/target_syscall.h
A configs/targets/riscv64-bsd-user.mak
M docs/specs/index.rst
M docs/specs/pci-ids.rst
A docs/specs/riscv-iommu.rst
M docs/system/riscv/virt.rst
M hw/intc/riscv_imsic.c
M hw/riscv/Kconfig
M hw/riscv/boot.c
M hw/riscv/meson.build
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
A hw/riscv/riscv-iommu-bits.h
A hw/riscv/riscv-iommu-pci.c
A hw/riscv/riscv-iommu.c
A hw/riscv/riscv-iommu.h
M hw/riscv/shakti_c.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
A hw/riscv/trace-events
A hw/riscv/trace.h
M hw/riscv/virt.c
M include/exec/memattrs.h
M include/hw/pci/pci.h
M include/hw/riscv/boot.h
A include/hw/riscv/iommu.h
M meson.build
M target/riscv/Kconfig
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/debug.c
M target/riscv/debug.h
M target/riscv/kvm/kvm-cpu.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/time_helper.c
M target/riscv/vector_helper.c
A tests/data/acpi/riscv64/virt/SRAT.numamem
M tests/qtest/bios-tables-test.c
M tests/qtest/libqos/meson.build
A tests/qtest/libqos/riscv-iommu.c
A tests/qtest/libqos/riscv-iommu.h
M tests/qtest/meson.build
A tests/qtest/riscv-iommu-test.c
M util/cpuinfo-riscv.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20240912-1' of
https://github.com/alistair23/qemu into staging
RISC-V PR for 9.2
* Add a property to set vl to ceil(AVL/2)
* Enable numamem testing for RISC-V
* Consider MISA bit choice in implied rule
* Fix the za64rs priv spec requirements
* Enable Bit Manip for OpenTitan Ibex CPU
* Fix the group bit setting of AIA with KVM
* Stop timer with infinite timecmp
* Add 'fcsr' register to QEMU log as a part of F extension
* Fix riscv64 build on musl libc
* Add preliminary textra trigger CSR functions
* RISC-V IOMMU support
* RISC-V bsd-user support
* Respect firmware ELF entry point
* Add Svvptc extension support
* Fix masking of rv32 physical address
* Fix linking problem with semihosting disabled
* Fix IMSIC interrupt state updates
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# gpg: Signature made Thu 12 Sep 2024 06:22:28 BST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20240912-1' of https://github.com/alistair23/qemu:
(47 commits)
hw/intc: riscv-imsic: Fix interrupt state updates.
target/riscv/cpu_helper: Fix linking problem with semihosting disabled
target/riscv32: Fix masking of physical address
target: riscv: Add Svvptc extension support
hw/riscv: Respect firmware ELF entry point
bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV
bsd-user: Implement 'get_mcontext' for RISC-V
bsd-user: Implement RISC-V signal trampoline setup functions
bsd-user: Define RISC-V signal handling structures and constants
bsd-user: Add generic RISC-V64 target definitions
bsd-user: Define RISC-V system call structures and constants
bsd-user: Define RISC-V VM parameters and helper functions
bsd-user: Add RISC-V thread setup and initialization support
bsd-user: Implement RISC-V sysarch system call emulation
bsd-user: Add RISC-V signal trampoline setup function
bsd-user: Define RISC-V register structures and register copying
bsd-user: Add RISC-V ELF definitions and hardware capability detection
bsd-user: Implement RISC-V TLS register setup
bsd-user: Implement RISC-V CPU register cloning and reset functions
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/3baa3c9d62bb...b620c1c6a407
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