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[Qemu-commits] [qemu/qemu] 6a0e10: hw/s390/ccw-device: Convert to three-
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 6a0e10: hw/s390/ccw-device: Convert to three-phase reset |
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Date: |
Fri, 13 Sep 2024 11:05:00 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 6a0e10b76b68e2f412746a1d5ed7d6efee804864
https://github.com/qemu/qemu/commit/6a0e10b76b68e2f412746a1d5ed7d6efee804864
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/s390x/ccw-device.c
Log Message:
-----------
hw/s390/ccw-device: Convert to three-phase reset
Convert the TYPE_CCW_DEVICE to three-phase reset. This is a
device class which is subclassed, so it needs to be three-phase
before we can convert the subclass.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-id: 20240830145812.1967042-2-peter.maydell@linaro.org
Commit: 6affa00d6ebebf24485667fe146470b0d6feb90d
https://github.com/qemu/qemu/commit/6affa00d6ebebf24485667fe146470b0d6feb90d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/s390x/virtio-ccw.c
M hw/s390x/virtio-ccw.h
Log Message:
-----------
hw/s390/virtio-ccw: Convert to three-phase reset
Convert the virtio-ccw code to three-phase reset. This allows us to
remove a call to device_class_set_parent_reset(), replacing it with
the three-phase equivalent resettable_class_set_parent_phases().
Removing all the device_class_set_parent_reset() uses will allow us
to remove some of the glue code that interworks between three-phase
and legacy reset.
This is a simple conversion, with no behavioural changes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240830145812.1967042-3-peter.maydell@linaro.org
Commit: cf7f61d13f28f32d0b14abb70ce1bd9e41623b2e
https://github.com/qemu/qemu/commit/cf7f61d13f28f32d0b14abb70ce1bd9e41623b2e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M docs/devel/reset.rst
M include/hw/resettable.h
M target/s390x/cpu.c
M target/s390x/cpu.h
M target/s390x/sigp.c
Log Message:
-----------
target/s390: Convert CPU to Resettable interface
Convert the s390 CPU to the Resettable interface. This is slightly
more involved than the other CPU types were (see commits
9130cade5fc22..d66e64dd006df) because S390 has its own set of
different kinds of reset with different behaviours that it needs to
trigger.
We handle this by adding these reset types to the Resettable
ResetType enum. Now instead of having an underlying implementation
of reset that is s390-specific and which might be called either
directly or via the DeviceClass::reset method, we can implement only
the Resettable hold phase method, and have the places that need to
trigger an s390-specific reset type do so by calling
resettable_reset().
The other option would have been to smuggle in the s390 reset
type via, for instance, a field in the CPU state that we set
in s390_do_cpu_initial_reset() etc and then examined in the
reset method, but doing it this way seems cleaner.
The motivation for this change is that this is the last caller
of the legacy device_class_set_parent_reset() function, and
removing that will let us clean up some glue code that we added
for the transition to three-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-id: 20240830145812.1967042-4-peter.maydell@linaro.org
Commit: 5313a0a41eedb5f5b0145657fb3aad516e5216f2
https://github.com/qemu/qemu/commit/5313a0a41eedb5f5b0145657fb3aad516e5216f2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/core/qdev.c
M include/hw/qdev-core.h
Log Message:
-----------
hw: Remove device_class_set_parent_reset()
There are no callers of device_class_set_parent_reset() left in the tree,
as they've all been converted to use three-phase reset and the
corresponding resettable_class_set_parent_phases() function.
Remove device_class_set_parent_reset().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240830145812.1967042-5-peter.maydell@linaro.org
Commit: 349ecf61e8c9d5b4f21dab80b37733fe73be5cfe
https://github.com/qemu/qemu/commit/349ecf61e8c9d5b4f21dab80b37733fe73be5cfe
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M target/alpha/cpu.h
M target/hppa/cpu.h
Log Message:
-----------
target/alpha, hppa: Remove unused parent_reset fields
The Alpha and HPPA CPU class structs include a 'parent_reset'
field which is never used; delete them.
(These targets don't seem to implement reset at all; if they did they
should do it using the three-phase reset mechanism, which uses a
'ResettablePhases parent_phases' field instead of the old
'DeviceReset parent_reset' field.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240830145812.1967042-6-peter.maydell@linaro.org
Commit: 134e0944f473c4d87a67f7e6ec70f0205a8e30c7
https://github.com/qemu/qemu/commit/134e0944f473c4d87a67f7e6ec70f0205a8e30c7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/core/qdev.c
M include/hw/qdev-core.h
A scripts/coccinelle/device-reset.cocci
Log Message:
-----------
hw: Define new device_class_set_legacy_reset()
Define a device_class_set_legacy_reset() function which
sets the DeviceClass::reset field. This serves two purposes:
* it makes it clearer to the person writing code that
DeviceClass::reset is now legacy and they should look for
the new alternative (which is Resettable)
* it makes it easier to rename the reset field (which in turn
makes it easier to find places that call it)
The Coccinelle script can be used to automatically convert code that
was doing an open-coded assignment to DeviceClass::reset to call
device_class_set_legacy_reset() instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240830145812.1967042-7-peter.maydell@linaro.org
Commit: e3d0814368d00e7985c31edf5d0cfce45972d4be
https://github.com/qemu/qemu/commit/e3d0814368d00e7985c31edf5d0cfce45972d4be
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/acpi/erst.c
M hw/acpi/piix4.c
M hw/adc/aspeed_adc.c
M hw/adc/max111x.c
M hw/adc/stm32f2xx_adc.c
M hw/adc/zynq-xadc.c
M hw/arm/armsse.c
M hw/arm/highbank.c
M hw/arm/musicpal.c
M hw/arm/pxa2xx.c
M hw/arm/strongarm.c
M hw/audio/ac97.c
M hw/audio/cs4231.c
M hw/audio/cs4231a.c
M hw/audio/es1370.c
M hw/audio/hda-codec.c
M hw/audio/intel-hda.c
M hw/audio/marvell_88w8618.c
M hw/audio/pl041.c
M hw/audio/via-ac97.c
M hw/block/fdc-isa.c
M hw/block/fdc-sysbus.c
M hw/block/m25p80.c
M hw/block/nand.c
M hw/block/onenand.c
M hw/block/pflash_cfi01.c
M hw/block/pflash_cfi02.c
M hw/block/swim.c
M hw/char/avr_usart.c
M hw/char/cmsdk-apb-uart.c
M hw/char/digic-uart.c
M hw/char/escc.c
M hw/char/etraxfs_ser.c
M hw/char/exynos4210_uart.c
M hw/char/goldfish_tty.c
M hw/char/grlib_apbuart.c
M hw/char/ibex_uart.c
M hw/char/imx_serial.c
M hw/char/mcf_uart.c
M hw/char/mchp_pfsoc_mmuart.c
M hw/char/nrf51_uart.c
M hw/char/pl011.c
M hw/char/renesas_sci.c
M hw/char/sclpconsole-lm.c
M hw/char/sclpconsole.c
M hw/char/sh_serial.c
M hw/char/shakti_uart.c
M hw/char/stm32f2xx_usart.c
M hw/char/xilinx_uartlite.c
M hw/core/or-irq.c
M hw/core/qdev.c
M hw/cxl/switch-mailbox-cci.c
M hw/display/artist.c
M hw/display/ati.c
M hw/display/bcm2835_fb.c
M hw/display/cg3.c
M hw/display/dpcd.c
M hw/display/exynos4210_fimd.c
M hw/display/g364fb.c
M hw/display/i2c-ddc.c
M hw/display/jazz_led.c
M hw/display/macfb.c
M hw/display/qxl.c
M hw/display/sii9022.c
M hw/display/sm501.c
M hw/display/tcx.c
M hw/display/vga-isa.c
M hw/display/vga-mmio.c
M hw/display/vga-pci.c
M hw/display/vmware_vga.c
M hw/display/xlnx_dp.c
M hw/dma/bcm2835_dma.c
M hw/dma/i8257.c
M hw/dma/pl080.c
M hw/dma/pl330.c
M hw/dma/rc4030.c
M hw/dma/sparc32_dma.c
M hw/dma/xilinx_axidma.c
M hw/dma/xlnx-zdma.c
M hw/dma/xlnx-zynq-devcfg.c
M hw/dma/xlnx_csu_dma.c
M hw/dma/xlnx_dpdma.c
M hw/fsi/aspeed_apb2opb.c
M hw/fsi/fsi-master.c
M hw/fsi/fsi.c
M hw/fsi/lbus.c
M hw/gpio/aspeed_gpio.c
M hw/gpio/bcm2835_gpio.c
M hw/gpio/bcm2838_gpio.c
M hw/gpio/gpio_key.c
M hw/gpio/imx_gpio.c
M hw/gpio/max7310.c
M hw/gpio/mpc8xxx.c
M hw/gpio/nrf51_gpio.c
M hw/gpio/omap_gpio.c
M hw/gpio/pca9552.c
M hw/gpio/pca9554.c
M hw/gpio/pcf8574.c
M hw/gpio/sifive_gpio.c
M hw/hyperv/hyperv.c
M hw/hyperv/vmbus.c
M hw/i2c/aspeed_i2c.c
M hw/i2c/bcm2835_i2c.c
M hw/i2c/exynos4210_i2c.c
M hw/i2c/imx_i2c.c
M hw/i2c/microbit_i2c.c
M hw/i2c/mpc_i2c.c
M hw/i2c/omap_i2c.c
M hw/i2c/ppc4xx_i2c.c
M hw/i2c/smbus_eeprom.c
M hw/i386/amd_iommu.c
M hw/i386/intel_iommu.c
M hw/i386/kvm/i8254.c
M hw/i386/kvm/i8259.c
M hw/i386/kvm/ioapic.c
M hw/i386/kvm/xen_overlay.c
M hw/i386/port92.c
M hw/i386/vapic.c
M hw/i386/vmmouse.c
M hw/i386/xen/xen_platform.c
M hw/ide/ahci.c
M hw/ide/cmd646.c
M hw/ide/ich.c
M hw/ide/isa.c
M hw/ide/macio.c
M hw/ide/microdrive.c
M hw/ide/mmio.c
M hw/ide/piix.c
M hw/ide/sii3112.c
M hw/ide/via.c
M hw/input/adb-kbd.c
M hw/input/adb-mouse.c
M hw/input/lm832x.c
M hw/input/pckbd.c
M hw/intc/allwinner-a10-pic.c
M hw/intc/apic_common.c
M hw/intc/armv7m_nvic.c
M hw/intc/aspeed_intc.c
M hw/intc/aspeed_vic.c
M hw/intc/bcm2835_ic.c
M hw/intc/bcm2836_control.c
M hw/intc/exynos4210_combiner.c
M hw/intc/goldfish_pic.c
M hw/intc/grlib_irqmp.c
M hw/intc/heathrow_pic.c
M hw/intc/i8259.c
M hw/intc/imx_avic.c
M hw/intc/imx_gpcv2.c
M hw/intc/ioapic.c
M hw/intc/loongarch_extioi.c
M hw/intc/loongarch_pch_pic.c
M hw/intc/m68k_irqc.c
M hw/intc/omap_intc.c
M hw/intc/openpic.c
M hw/intc/openpic_kvm.c
M hw/intc/pl190.c
M hw/intc/ppc-uic.c
M hw/intc/s390_flic.c
M hw/intc/s390_flic_kvm.c
M hw/intc/sifive_plic.c
M hw/intc/slavio_intctl.c
M hw/intc/xlnx-pmu-iomod-intc.c
M hw/intc/xlnx-zynqmp-ipi.c
M hw/isa/lpc_ich9.c
M hw/isa/pc87312.c
M hw/isa/piix.c
M hw/isa/vt82c686.c
M hw/m68k/mcf5206.c
M hw/m68k/mcf_intc.c
M hw/m68k/next-cube.c
M hw/m68k/next-kbd.c
M hw/mem/cxl_type3.c
M hw/misc/a9scu.c
M hw/misc/allwinner-cpucfg.c
M hw/misc/allwinner-h3-ccu.c
M hw/misc/allwinner-h3-dramc.c
M hw/misc/allwinner-h3-sysctrl.c
M hw/misc/allwinner-r40-ccu.c
M hw/misc/allwinner-r40-dramc.c
M hw/misc/allwinner-sid.c
M hw/misc/allwinner-sramc.c
M hw/misc/applesmc.c
M hw/misc/arm_l2x0.c
M hw/misc/arm_sysctl.c
M hw/misc/armsse-cpu-pwrctrl.c
M hw/misc/armsse-mhu.c
M hw/misc/aspeed_hace.c
M hw/misc/aspeed_i3c.c
M hw/misc/aspeed_lpc.c
M hw/misc/aspeed_peci.c
M hw/misc/aspeed_sbc.c
M hw/misc/aspeed_scu.c
M hw/misc/aspeed_sdmc.c
M hw/misc/aspeed_xdma.c
M hw/misc/avr_power.c
M hw/misc/bcm2835_cprman.c
M hw/misc/bcm2835_mbox.c
M hw/misc/bcm2835_mphi.c
M hw/misc/bcm2835_powermgt.c
M hw/misc/bcm2835_rng.c
M hw/misc/bcm2835_thermal.c
M hw/misc/eccmemctl.c
M hw/misc/exynos4210_clk.c
M hw/misc/exynos4210_pmu.c
M hw/misc/exynos4210_rng.c
M hw/misc/imx25_ccm.c
M hw/misc/imx31_ccm.c
M hw/misc/imx6_ccm.c
M hw/misc/imx6_src.c
M hw/misc/imx6ul_ccm.c
M hw/misc/imx7_ccm.c
M hw/misc/imx7_snvs.c
M hw/misc/imx7_src.c
M hw/misc/imx_rngc.c
M hw/misc/iotkit-secctl.c
M hw/misc/iotkit-sysctl.c
M hw/misc/ivshmem.c
M hw/misc/lasi.c
M hw/misc/led.c
M hw/misc/macio/cuda.c
M hw/misc/macio/gpio.c
M hw/misc/macio/mac_dbdma.c
M hw/misc/macio/pmu.c
M hw/misc/mips_cmgcr.c
M hw/misc/mips_cpc.c
M hw/misc/mips_itu.c
M hw/misc/mps2-fpgaio.c
M hw/misc/mps2-scc.c
M hw/misc/msf2-sysreg.c
M hw/misc/nrf51_rng.c
M hw/misc/pci-testdev.c
M hw/misc/sifive_e_aon.c
M hw/misc/sifive_u_prci.c
M hw/misc/slavio_misc.c
M hw/misc/stm32f2xx_syscfg.c
M hw/misc/stm32f4xx_exti.c
M hw/misc/stm32f4xx_syscfg.c
M hw/misc/tz-mpc.c
M hw/misc/tz-msc.c
M hw/misc/tz-ppc.c
M hw/misc/virt_ctrl.c
M hw/misc/xlnx-versal-cfu.c
M hw/net/allwinner-sun8i-emac.c
M hw/net/allwinner_emac.c
M hw/net/cadence_gem.c
M hw/net/can/can_kvaser_pci.c
M hw/net/can/can_mioe3680_pci.c
M hw/net/can/can_pcm3680_pci.c
M hw/net/can/ctucan_pci.c
M hw/net/can/xlnx-versal-canfd.c
M hw/net/dp8393x.c
M hw/net/etraxfs_eth.c
M hw/net/fsl_etsec/etsec.c
M hw/net/ftgmac100.c
M hw/net/imx_fec.c
M hw/net/lan9118.c
M hw/net/lance.c
M hw/net/lasi_i82596.c
M hw/net/mcf_fec.c
M hw/net/mipsnet.c
M hw/net/msf2-emac.c
M hw/net/npcm7xx_emc.c
M hw/net/npcm_gmac.c
M hw/net/opencores_eth.c
M hw/net/pcnet-pci.c
M hw/net/rocker/rocker.c
M hw/net/rtl8139.c
M hw/net/smc91c111.c
M hw/net/stellaris_enet.c
M hw/net/sungem.c
M hw/net/sunhme.c
M hw/net/tulip.c
M hw/net/vmxnet3.c
M hw/net/xilinx_axienet.c
M hw/net/xilinx_ethlite.c
M hw/nvme/ctrl.c
M hw/nvram/eeprom_at24c.c
M hw/nvram/fw_cfg.c
M hw/nvram/mac_nvram.c
M hw/nvram/nrf51_nvm.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_upstream.c
M hw/pci-bridge/i82801b11.c
M hw/pci-bridge/pci_bridge_dev.c
M hw/pci-bridge/pci_expander_bridge.c
M hw/pci-bridge/pcie_pci_bridge.c
M hw/pci-bridge/simba.c
M hw/pci-bridge/xio3130_downstream.c
M hw/pci-bridge/xio3130_upstream.c
M hw/pci-host/astro.c
M hw/pci-host/designware.c
M hw/pci-host/dino.c
M hw/pci-host/gt64120.c
M hw/pci-host/mv64361.c
M hw/pci-host/ppc440_pcix.c
M hw/pci-host/q35.c
M hw/pci-host/sabre.c
M hw/pci-host/versatile.c
M hw/pci-host/xilinx-pcie.c
M hw/ppc/pnv_psi.c
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/ppc4xx_sdram.c
M hw/ppc/ppce500_spin.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M hw/remote/proxy.c
M hw/rtc/allwinner-rtc.c
M hw/rtc/aspeed_rtc.c
M hw/rtc/ds1338.c
M hw/rtc/exynos4210_rtc.c
M hw/rtc/goldfish_rtc.c
M hw/rtc/ls7a_rtc.c
M hw/rtc/m48t59-isa.c
M hw/rtc/m48t59.c
M hw/rtc/xlnx-zynqmp-rtc.c
M hw/s390x/event-facility.c
M hw/s390x/ipl.c
M hw/s390x/s390-pci-bus.c
M hw/s390x/sclpquiesce.c
M hw/scsi/esp-pci.c
M hw/scsi/esp.c
M hw/scsi/lsi53c895a.c
M hw/scsi/megasas.c
M hw/scsi/mptsas.c
M hw/scsi/scsi-disk.c
M hw/scsi/scsi-generic.c
M hw/scsi/vmw_pvscsi.c
M hw/sd/allwinner-sdhost.c
M hw/sd/aspeed_sdhci.c
M hw/sd/bcm2835_sdhost.c
M hw/sd/cadence_sdhci.c
M hw/sd/npcm7xx_sdhci.c
M hw/sd/pl181.c
M hw/sd/pxa2xx_mmci.c
M hw/sd/sd.c
M hw/sd/sdhci.c
M hw/sd/ssi-sd.c
M hw/sensor/dps310.c
M hw/sensor/emc141x.c
M hw/sensor/lsm303dlhc_mag.c
M hw/sparc/sun4m_iommu.c
M hw/sparc64/sun4u_iommu.c
M hw/ssi/aspeed_smc.c
M hw/ssi/bcm2835_spi.c
M hw/ssi/ibex_spi_host.c
M hw/ssi/imx_spi.c
M hw/ssi/mss-spi.c
M hw/ssi/pl022.c
M hw/ssi/pnv_spi.c
M hw/ssi/sifive_spi.c
M hw/ssi/stm32f2xx_spi.c
M hw/ssi/xilinx_spi.c
M hw/ssi/xilinx_spips.c
M hw/ssi/xlnx-versal-ospi.c
M hw/timer/a9gtimer.c
M hw/timer/allwinner-a10-pit.c
M hw/timer/arm_mptimer.c
M hw/timer/armv7m_systick.c
M hw/timer/aspeed_timer.c
M hw/timer/avr_timer16.c
M hw/timer/bcm2835_systmr.c
M hw/timer/cmsdk-apb-dualtimer.c
M hw/timer/cmsdk-apb-timer.c
M hw/timer/digic-timer.c
M hw/timer/exynos4210_mct.c
M hw/timer/exynos4210_pwm.c
M hw/timer/grlib_gptimer.c
M hw/timer/hpet.c
M hw/timer/i8254.c
M hw/timer/ibex_timer.c
M hw/timer/imx_epit.c
M hw/timer/imx_gpt.c
M hw/timer/nrf51_timer.c
M hw/timer/renesas_cmt.c
M hw/timer/renesas_tmr.c
M hw/timer/sifive_pwm.c
M hw/timer/slavio_timer.c
M hw/timer/sse-counter.c
M hw/timer/sse-timer.c
M hw/timer/stm32f2xx_timer.c
M hw/tpm/tpm_tis_i2c.c
M hw/tpm/tpm_tis_isa.c
M hw/tpm/tpm_tis_sysbus.c
M hw/tricore/tricore_testdevice.c
M hw/usb/hcd-dwc3.c
M hw/usb/hcd-ehci-pci.c
M hw/usb/hcd-ehci-sysbus.c
M hw/usb/hcd-ohci-pci.c
M hw/usb/hcd-ohci-sysbus.c
M hw/usb/hcd-uhci.c
M hw/usb/hcd-xhci-pci.c
M hw/usb/hcd-xhci-sysbus.c
M hw/usb/hcd-xhci.c
M hw/usb/imx-usb-phy.c
M hw/usb/tusb6010.c
M hw/vfio/ap.c
M hw/vfio/ccw.c
M hw/vfio/pci.c
M hw/virtio/virtio-mmio.c
M hw/watchdog/cmsdk-apb-watchdog.c
M hw/watchdog/sbsa_gwdt.c
M hw/watchdog/wdt_aspeed.c
M hw/watchdog/wdt_diag288.c
M hw/watchdog/wdt_i6300esb.c
M hw/watchdog/wdt_ib700.c
M hw/watchdog/wdt_imx2.c
Log Message:
-----------
hw: Use device_class_set_legacy_reset() instead of opencoding
Use device_class_set_legacy_reset() instead of opencoding an
assignment to DeviceClass::reset. This change was produced
with:
spatch --macro-file scripts/cocci-macro-file.h \
--sp-file scripts/coccinelle/device-reset.cocci \
--keep-comments --smpl-spacing --in-place --dir hw
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240830145812.1967042-8-peter.maydell@linaro.org
Commit: 1000872dde2fc089823df7394ca2c9690734091a
https://github.com/qemu/qemu/commit/1000872dde2fc089823df7394ca2c9690734091a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/core/qdev.c
M include/hw/qdev-core.h
Log Message:
-----------
hw: Rename DeviceClass::reset field to legacy_reset
Rename the DeviceClass::reset field to legacy_reset; this is helpful
both in flagging up that it's best not used in new code and in
making it easy to search for where it's being used still.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240830145812.1967042-9-peter.maydell@linaro.org
Commit: b5fe9bf296ea5604a16f6dfb4777bfce56cd48c0
https://github.com/qemu/qemu/commit/b5fe9bf296ea5604a16f6dfb4777bfce56cd48c0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/core/qdev.c
Log Message:
-----------
hw: Remove device_phases_reset()
Currently we have transitional machinery between legacy reset
and three phase reset that works in two directions:
* if you invoke three phase reset on a device which has set
the DeviceClass::legacy_reset method, we detect this in
device_get_transitional_reset() and arrange that we call
the legacy_reset method during the hold phase of reset
* if you invoke legacy reset on a device which implements
three phase reset, the default legacy_reset method is
device_phases_reset(), which does a three-phase reset
of the device
However, we have now eliminated all the places which could invoke
legacy reset on a device, which means that the function
device_phases_reset() is never called -- it serves only as the value
of DeviceClass::legacy_reset that indicates that the subclass never
overrode the legacy reset method. So we can delete it, and instead
check for legacy_reset != NULL.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240830145812.1967042-10-peter.maydell@linaro.org
Commit: 5fdb6cd27211eff4d5b607972ac1d1d02688e905
https://github.com/qemu/qemu/commit/5fdb6cd27211eff4d5b607972ac1d1d02688e905
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/core/qdev.c
Log Message:
-----------
hw/core/qdev: Simplify legacy_reset handling
Now that all devices which still implement a the legacy reset method
register it via device_class_legacy_reset(), we can simplify the
handling of these devices. Instead of using the complex
Resettable::get_transitional_function machinery, we register a hold
phase method which invokes the DeviceClass::legacy_reset method.
This will allow us to remove all the get_transitional_function
handling from resettable.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240830145812.1967042-11-peter.maydell@linaro.org
Commit: b313487566e23ce91dac427f0604556a888e9713
https://github.com/qemu/qemu/commit/b313487566e23ce91dac427f0604556a888e9713
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/core/resettable.c
M include/hw/resettable.h
Log Message:
-----------
hw/core/resettable: Remove transitional_function machinery
We used to need the transitional_function machinery to handle bus
classes and device classes which still used their legacy reset
handling. We have now converted all bus classes to three phase
reset, and simplified the device class legacy reset so it is just an
adapting wrapper function around registration of a hold phase method.
There are therefore no more users of the transitional_function
machinery and we can remove it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240830145812.1967042-12-peter.maydell@linaro.org
Commit: 6a8703aecb152ef4324dc95273eca864b78b3837
https://github.com/qemu/qemu/commit/6a8703aecb152ef4324dc95273eca864b78b3837
Author: Johannes Stoelp <johannes.stoelp@googlemail.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M accel/kvm/kvm-all.c
M accel/kvm/trace-events
M include/sysemu/kvm.h
M include/sysemu/kvm_int.h
M target/i386/kvm/kvm.c
Log Message:
-----------
kvm: Use 'unsigned long' for request argument in functions wrapping ioctl()
Change the data type of the ioctl _request_ argument from 'int' to
'unsigned long' for the various accel/kvm functions which are
essentially wrappers around the ioctl() syscall.
The correct type for ioctl()'s 'request' argument is confused:
* POSIX defines the request argument as 'int'
* glibc uses 'unsigned long' in the prototype in sys/ioctl.h
* the glibc info documentation uses 'int'
* the Linux manpage uses 'unsigned long'
* the Linux implementation of the syscall uses 'unsigned int'
If we wrap ioctl() with another function which uses 'int' as the
type for the request argument, then requests with the 0x8000_0000
bit set will be sign-extended when the 'int' is cast to
'unsigned long' for the call to ioctl().
On x86_64 one such example is the KVM_IRQ_LINE_STATUS request.
Bit requests with the _IOC_READ direction bit set, will have the high
bit set.
Fortunately the Linux Kernel truncates the upper 32bit of the request
on 64bit machines (because it uses 'unsigned int', and see also Linus
Torvalds' comments in
https://sourceware.org/bugzilla/show_bug.cgi?id=14362 )
so this doesn't cause active problems for us. However it is more
consistent to follow the glibc ioctl() prototype when we define
functions that are essentially wrappers around ioctl().
This resolves a Coverity issue where it points out that in
kvm_get_xsave() we assign a value (KVM_GET_XSAVE or KVM_GET_XSAVE2)
to an 'int' variable which can't hold it without overflow.
Resolves: Coverity CID 1547759
Signed-off-by: Johannes Stoelp <johannes.stoelp@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-id: 20240815122747.3053871-1-peter.maydell@linaro.org
[PMM: Rebased patch, adjusted commit message, included note about
Coverity fix, updated the type of the local var in kvm_get_xsave,
updated the comment in the KVMState struct definition]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 81e3d93a9e3b3baa0e73e674ca3d1b93a672cc6d
https://github.com/qemu/qemu/commit/81e3d93a9e3b3baa0e73e674ca3d1b93a672cc6d
Author: Danny Canter <danny_canter@apple.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/arm/virt.c
M include/hw/boards.h
Log Message:
-----------
hw/boards: Add hvf_get_physical_address_range to MachineClass
This addition will be necessary for some HVF related work to follow.
For HVF on ARM there exists a set of APIs in macOS 13 to be able to
adjust the IPA size for a given VM. This is useful as by default HVF
uses 36 bits as the IPA size, so to support guests with > 64GB of RAM
we'll need to reach for this.
To have all the info necessary to carry this out however, we need some
plumbing to be able to grab the memory map and compute the highest GPA
prior to creating the VM. This is almost exactly like what kvm_type is
used for on ARM today, and is also what this will be used for. We will
compute the highest GPA and find what IPA size we'd need to satisfy this,
and if it's valid (macOS today caps at 40b) we'll set this to be the IPA
size in coming patches. This new method is only needed (today at least)
on ARM, and obviously only for HVF/macOS, so admittedly it is much less
generic than kvm_type today, but it seemed a somewhat sane way to get
the information we need from the memmap at VM creation time.
Signed-off-by: Danny Canter <danny_canter@apple.com>
Message-id: 20240828111552.93482-2-danny_canter@apple.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: removed explicit setting of field to NULL on x86]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2c760670af5f013d99d50f627275a482fd491e3f
https://github.com/qemu/qemu/commit/2c760670af5f013d99d50f627275a482fd491e3f
Author: Danny Canter <danny_canter@apple.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M accel/hvf/hvf-accel-ops.c
M include/sysemu/hvf_int.h
M target/arm/hvf/hvf.c
M target/i386/hvf/hvf.c
Log Message:
-----------
hvf: Split up hv_vm_create logic per arch
This is preliminary work to split up hv_vm_create
logic per platform so we can support creating VMs
with > 64GB of RAM on Apple Silicon machines. This
is done via ARM HVF's hv_vm_config_create() (and
other APIs that modify this config that will be
coming in future patches). This should have no
behavioral difference at all as hv_vm_config_create()
just assigns the same default values as if you just
passed NULL to the function.
Signed-off-by: Danny Canter <danny_canter@apple.com>
Message-id: 20240828111552.93482-3-danny_canter@apple.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d54ffa54fbe0691f8e953b867cbe65642efbdf67
https://github.com/qemu/qemu/commit/d54ffa54fbe0691f8e953b867cbe65642efbdf67
Author: Danny Canter <danny_canter@apple.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M accel/hvf/hvf-accel-ops.c
M hw/arm/virt.c
M target/arm/hvf/hvf.c
M target/arm/hvf_arm.h
M target/arm/internals.h
M target/arm/ptw.c
Log Message:
-----------
hvf: arm: Implement and use hvf_get_physical_address_range
This patch's main focus is to use the previously added
hvf_get_physical_address_range to inform VM creation
about the IPA size we need for the VM, so we can extend
the default 36b IPA size and support VMs with 64+GB of
RAM. This is done by freezing the memory map, computing
the highest GPA and then (depending on if the platform
supports an IPA size that large) telling the kernel to
use a size >= for the VM. In pursuit of this a couple of
things related to how we handle the physical address range
we expose to guests were altered, but for an explanation of
what we were doing:
Today, to get the IPA size we were reading id_aa64mmfr0_el1's
PARange field from a newly made vcpu. Unfortunately, HVF just
returns the hosts PARange directly for the initial value and
not the IPA size that will actually back the VM, so we believe
we have much more address space than we actually do today it seems.
Starting in macOS 13.0 some APIs were introduced to be able to
query the maximum IPA size the kernel supports, and to set the IPA
size for a given VM. However, this still has a couple of issues
on < macOS 15. Up until macOS 15 (and if the hardware supported
it) the max IPA size was 39 bits which is not a valid PARange
value, so we can't clamp down what we advertise in the vcpu's
id_aa64mmfr0_el1 to our IPA size. Starting in macOS 15 however,
the maximum IPA size is 40 bits (if it's supported in the hardware
as well) which is also a valid PARange value so we can set our IPA
size to the maximum as well as clamp down the PARange we advertise
to the guest. This allows VMs with 64+ GB of RAM and should fix the
oddness of the PARange situation as well.
Signed-off-by: Danny Canter <danny_canter@apple.com>
Message-id: 20240828111552.93482-4-danny_canter@apple.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 676624d757abe0adcfa648ed3d4d44697997382f
https://github.com/qemu/qemu/commit/676624d757abe0adcfa648ed3d4d44697997382f
Author: Alireza Sanaee <alireza.sanaee@huawei.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu64.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm/tcg: refine cache descriptions with a wrapper
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One function `make_ccsidr` supports
two cases by carrying a parameter as FORMAT that can be LEGACY and
CCIDX which determines the specification of the register.
For CCSIDR register, 32 bit version follows specification [1].
Conversely, 64 bit version follows specification [2].
[1] B4.1.19, ARM Architecture Reference Manual ARMv7-A and ARMv7-R
edition, https://developer.arm.com/documentation/ddi0406
[2] D23.2.29, ARM Architecture Reference Manual for A-profile Architecture,
https://developer.arm.com/documentation/ddi0487/latest/
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240903144550.280-1-alireza.sanaee@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2215e297b9af4a42fefd1c014f7a3048995cea97
https://github.com/qemu/qemu/commit/2215e297b9af4a42fefd1c014f7a3048995cea97
Author: Doug Brown <doug@schmorgal.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/net/can/xlnx-versal-canfd.c
Log Message:
-----------
hw/net/can/xlnx-versal-canfd: Fix interrupt level
The interrupt level should be 0 or 1. The existing code was using the
interrupt flags to determine the level. In the only machine currently
supported (xlnx-versal-virt), the GICv3 was masking off all bits except
bit 0 when applying it, resulting in the IRQ never being delivered.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Message-id: 20240827034927.66659-2-doug@schmorgal.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cd1e485facbeae99452a534c5d26e48bb69d7ecd
https://github.com/qemu/qemu/commit/cd1e485facbeae99452a534c5d26e48bb69d7ecd
Author: Doug Brown <doug@schmorgal.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/net/can/xlnx-versal-canfd.c
Log Message:
-----------
hw/net/can/xlnx-versal-canfd: Fix CAN FD flag check
When checking the QEMU_CAN_FRMF_TYPE_FD flag, we need to ignore other
potentially set flags. Before this change, received CAN FD frames from
SocketCAN weren't being recognized as CAN FD.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20240827034927.66659-3-doug@schmorgal.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 77dcbf16d971596261ddaa910f57ccceb48227b5
https://github.com/qemu/qemu/commit/77dcbf16d971596261ddaa910f57ccceb48227b5
Author: Doug Brown <doug@schmorgal.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/net/can/xlnx-versal-canfd.c
Log Message:
-----------
hw/net/can/xlnx-versal-canfd: Translate CAN ID registers
Previously the emulated CAN ID register was being set to the exact same
value stored in qemu_can_frame.can_id. This doesn't work correctly
because the Xilinx IP core uses a different bit arrangement than
qemu_can_frame for all of its ID registers. Correct this problem for
both RX and TX, including RX filtering.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Acked-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Message-id: 20240827034927.66659-4-doug@schmorgal.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7f34aae641ce1a2654c1a950aec4eab6f371a55d
https://github.com/qemu/qemu/commit/7f34aae641ce1a2654c1a950aec4eab6f371a55d
Author: Doug Brown <doug@schmorgal.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/net/can/xlnx-versal-canfd.c
Log Message:
-----------
hw/net/can/xlnx-versal-canfd: Handle flags correctly
Add support for QEMU_CAN_FRMF_ESI and QEMU_CAN_FRMF_BRS flags, and
ensure frame->flags is always initialized to 0.
Note that the Xilinx IP core doesn't allow manually setting the ESI bit
during transmits, so it's only implemented for the receive case.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Message-id: 20240827034927.66659-5-doug@schmorgal.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: be243e9ddb8f0ba149a1c51faee035c303be7eeb
https://github.com/qemu/qemu/commit/be243e9ddb8f0ba149a1c51faee035c303be7eeb
Author: Doug Brown <doug@schmorgal.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/net/can/xlnx-versal-canfd.c
Log Message:
-----------
hw/net/can/xlnx-versal-canfd: Fix byte ordering
The endianness of the CAN data was backwards in each group of 4 bytes.
For example, the following data:
00 11 22 33 44 55 66 77
was showing up like this:
33 22 11 00 77 66 55 44
Fix both the TX and RX code to put the data in the correct order.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Acked-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Message-id: 20240827034927.66659-6-doug@schmorgal.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 12d60ca09e5150b785d067566f49e330c68b2985
https://github.com/qemu/qemu/commit/12d60ca09e5150b785d067566f49e330c68b2985
Author: Doug Brown <doug@schmorgal.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/net/can/xlnx-versal-canfd.c
Log Message:
-----------
hw/net/can/xlnx-versal-canfd: Simplify DLC conversions
Use QEMU's helper functions can_dlc2len() and can_len2dlc() for
translating between the raw DLC value and the SocketCAN length value.
This also has the side effect of correctly handling received CAN FD
frames with a DLC of 0-8, which was broken previously.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20240827034927.66659-7-doug@schmorgal.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d4b668b799c5ce7ab7cc500707edff8af01ecf68
https://github.com/qemu/qemu/commit/d4b668b799c5ce7ab7cc500707edff8af01ecf68
Author: Doug Brown <doug@schmorgal.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/net/can/xlnx-versal-canfd.c
Log Message:
-----------
hw/net/can/xlnx-versal-canfd: Fix FIFO issues
The read index should not be changed when storing a new message into the
RX or TX FIFO. Changing it at this point will cause the reader to get
out of sync. The wrapping of the read index is already handled by the
pre-write functions for the FIFO status registers anyway.
Additionally, the calculation for wrapping the store index was off by
one, which caused new messages to be written to the wrong location in
the FIFO. This caused incorrect messages to be delivered.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20240827034927.66659-8-doug@schmorgal.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c009d715721861984c4987bcc78b7ee183e86d75
https://github.com/qemu/qemu/commit/c009d715721861984c4987bcc78b7ee183e86d75
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Remove Vikram Garhwal as maintainer
Vikram's email is bouncing, pause his maintainership until a new email is
provided.
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20240906181645.40359-2-francisco.iglesias@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: dbd1fbed1a0810862fd63b367504f3f01ad7dd6c
https://github.com/qemu/qemu/commit/dbd1fbed1a0810862fd63b367504f3f01ad7dd6c
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Update Xilinx Versal OSPI maintainer's email address
Update my xilinx.com email address to my amd.com address.
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20240906181645.40359-3-francisco.iglesias@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 02c5e065e6548b2961c47d6614492075fd4ad8f6
https://github.com/qemu/qemu/commit/02c5e065e6548b2961c47d6614492075fd4ad8f6
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add my-self as CAN maintainer
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20240906181645.40359-4-francisco.iglesias@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 110684c9a69a02cbabfbddcd3afa921826ad565c
https://github.com/qemu/qemu/commit/110684c9a69a02cbabfbddcd3afa921826ad565c
Author: Jan Klötzke <jan.kloetzke@kernkonzept.com>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M hw/intc/arm_gic.c
Log Message:
-----------
hw/intc/arm_gic: fix spurious level triggered interrupts
On GICv2 and later, level triggered interrupts are pending when either
the interrupt line is asserted or the interrupt was made pending by a
GICD_ISPENDRn write. Making a level triggered interrupt pending by
software persists until either the interrupt is acknowledged or cleared
by writing GICD_ICPENDRn. As long as the interrupt line is asserted,
the interrupt is pending in any case.
This logic is transparently implemented in gic_test_pending() for
GICv1 and GICv2. The function combines the "pending" irq_state flag
(used for edge triggered interrupts and software requests) and the
line status (tracked in the "level" field). However, we also
incorrectly set the pending flag on a guest write to GICD_ISENABLERn
if the line of a level triggered interrupt was asserted. This keeps
the interrupt pending even if the line is de-asserted after some
time.
This incorrect logic is a leftover of the initial 11MPCore GIC
implementation. That handles things slightly differently to the
architected GICv1 and GICv2. The 11MPCore TRM does not give a lot of
detail on the corner cases of its GIC's behaviour, and historically
we have not wanted to investigate exactly what it does in reality, so
QEMU's GIC model takes the approach of "retain our existing behaviour
for 11MPCore, and implement the architectural standard for later GIC
revisions".
On that basis, commit 8d999995e45c10 in 2013 is where we added the
"level-triggered interrupt with the line asserted" handling to
gic_test_pending(), and we deliberately kept the old behaviour of
gic_test_pending() for REV_11MPCORE. That commit should have added
the "only if 11MPCore" condition to the setting of the pending bit on
writes to GICD_ISENABLERn, but forgot it.
Add the missing "if REV_11MPCORE" condition, so that our behaviour
on GICv1 and GICv2 matches the GIC architecture requirements.
Cc: qemu-stable@nongnu.org
Fixes: 8d999995e45c10 ("arm_gic: Fix GIC pending behavior")
Signed-off-by: Jan Klötzke <jan.kloetzke@kernkonzept.com>
Message-id: 20240911114826.3558302-1-jan.kloetzke@kernkonzept.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: expanded comment a little and converted to coding-style form;
expanded commit message with the historical backstory]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 28ae3179fc52d2e4d870b635c4a412aab99759e7
https://github.com/qemu/qemu/commit/28ae3179fc52d2e4d870b635c4a412aab99759e7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-13 (Fri, 13 Sep 2024)
Changed paths:
M MAINTAINERS
M accel/hvf/hvf-accel-ops.c
M accel/kvm/kvm-all.c
M accel/kvm/trace-events
M docs/devel/reset.rst
M hw/acpi/erst.c
M hw/acpi/piix4.c
M hw/adc/aspeed_adc.c
M hw/adc/max111x.c
M hw/adc/stm32f2xx_adc.c
M hw/adc/zynq-xadc.c
M hw/arm/armsse.c
M hw/arm/highbank.c
M hw/arm/musicpal.c
M hw/arm/pxa2xx.c
M hw/arm/strongarm.c
M hw/arm/virt.c
M hw/audio/ac97.c
M hw/audio/cs4231.c
M hw/audio/cs4231a.c
M hw/audio/es1370.c
M hw/audio/hda-codec.c
M hw/audio/intel-hda.c
M hw/audio/marvell_88w8618.c
M hw/audio/pl041.c
M hw/audio/via-ac97.c
M hw/block/fdc-isa.c
M hw/block/fdc-sysbus.c
M hw/block/m25p80.c
M hw/block/nand.c
M hw/block/onenand.c
M hw/block/pflash_cfi01.c
M hw/block/pflash_cfi02.c
M hw/block/swim.c
M hw/char/avr_usart.c
M hw/char/cmsdk-apb-uart.c
M hw/char/digic-uart.c
M hw/char/escc.c
M hw/char/etraxfs_ser.c
M hw/char/exynos4210_uart.c
M hw/char/goldfish_tty.c
M hw/char/grlib_apbuart.c
M hw/char/ibex_uart.c
M hw/char/imx_serial.c
M hw/char/mcf_uart.c
M hw/char/mchp_pfsoc_mmuart.c
M hw/char/nrf51_uart.c
M hw/char/pl011.c
M hw/char/renesas_sci.c
M hw/char/sclpconsole-lm.c
M hw/char/sclpconsole.c
M hw/char/sh_serial.c
M hw/char/shakti_uart.c
M hw/char/stm32f2xx_usart.c
M hw/char/xilinx_uartlite.c
M hw/core/or-irq.c
M hw/core/qdev.c
M hw/core/resettable.c
M hw/cxl/switch-mailbox-cci.c
M hw/display/artist.c
M hw/display/ati.c
M hw/display/bcm2835_fb.c
M hw/display/cg3.c
M hw/display/dpcd.c
M hw/display/exynos4210_fimd.c
M hw/display/g364fb.c
M hw/display/i2c-ddc.c
M hw/display/jazz_led.c
M hw/display/macfb.c
M hw/display/qxl.c
M hw/display/sii9022.c
M hw/display/sm501.c
M hw/display/tcx.c
M hw/display/vga-isa.c
M hw/display/vga-mmio.c
M hw/display/vga-pci.c
M hw/display/vmware_vga.c
M hw/display/xlnx_dp.c
M hw/dma/bcm2835_dma.c
M hw/dma/i8257.c
M hw/dma/pl080.c
M hw/dma/pl330.c
M hw/dma/rc4030.c
M hw/dma/sparc32_dma.c
M hw/dma/xilinx_axidma.c
M hw/dma/xlnx-zdma.c
M hw/dma/xlnx-zynq-devcfg.c
M hw/dma/xlnx_csu_dma.c
M hw/dma/xlnx_dpdma.c
M hw/fsi/aspeed_apb2opb.c
M hw/fsi/fsi-master.c
M hw/fsi/fsi.c
M hw/fsi/lbus.c
M hw/gpio/aspeed_gpio.c
M hw/gpio/bcm2835_gpio.c
M hw/gpio/bcm2838_gpio.c
M hw/gpio/gpio_key.c
M hw/gpio/imx_gpio.c
M hw/gpio/max7310.c
M hw/gpio/mpc8xxx.c
M hw/gpio/nrf51_gpio.c
M hw/gpio/omap_gpio.c
M hw/gpio/pca9552.c
M hw/gpio/pca9554.c
M hw/gpio/pcf8574.c
M hw/gpio/sifive_gpio.c
M hw/hyperv/hyperv.c
M hw/hyperv/vmbus.c
M hw/i2c/aspeed_i2c.c
M hw/i2c/bcm2835_i2c.c
M hw/i2c/exynos4210_i2c.c
M hw/i2c/imx_i2c.c
M hw/i2c/microbit_i2c.c
M hw/i2c/mpc_i2c.c
M hw/i2c/omap_i2c.c
M hw/i2c/ppc4xx_i2c.c
M hw/i2c/smbus_eeprom.c
M hw/i386/amd_iommu.c
M hw/i386/intel_iommu.c
M hw/i386/kvm/i8254.c
M hw/i386/kvm/i8259.c
M hw/i386/kvm/ioapic.c
M hw/i386/kvm/xen_overlay.c
M hw/i386/port92.c
M hw/i386/vapic.c
M hw/i386/vmmouse.c
M hw/i386/xen/xen_platform.c
M hw/ide/ahci.c
M hw/ide/cmd646.c
M hw/ide/ich.c
M hw/ide/isa.c
M hw/ide/macio.c
M hw/ide/microdrive.c
M hw/ide/mmio.c
M hw/ide/piix.c
M hw/ide/sii3112.c
M hw/ide/via.c
M hw/input/adb-kbd.c
M hw/input/adb-mouse.c
M hw/input/lm832x.c
M hw/input/pckbd.c
M hw/intc/allwinner-a10-pic.c
M hw/intc/apic_common.c
M hw/intc/arm_gic.c
M hw/intc/armv7m_nvic.c
M hw/intc/aspeed_intc.c
M hw/intc/aspeed_vic.c
M hw/intc/bcm2835_ic.c
M hw/intc/bcm2836_control.c
M hw/intc/exynos4210_combiner.c
M hw/intc/goldfish_pic.c
M hw/intc/grlib_irqmp.c
M hw/intc/heathrow_pic.c
M hw/intc/i8259.c
M hw/intc/imx_avic.c
M hw/intc/imx_gpcv2.c
M hw/intc/ioapic.c
M hw/intc/loongarch_extioi.c
M hw/intc/loongarch_pch_pic.c
M hw/intc/m68k_irqc.c
M hw/intc/omap_intc.c
M hw/intc/openpic.c
M hw/intc/openpic_kvm.c
M hw/intc/pl190.c
M hw/intc/ppc-uic.c
M hw/intc/s390_flic.c
M hw/intc/s390_flic_kvm.c
M hw/intc/sifive_plic.c
M hw/intc/slavio_intctl.c
M hw/intc/xlnx-pmu-iomod-intc.c
M hw/intc/xlnx-zynqmp-ipi.c
M hw/isa/lpc_ich9.c
M hw/isa/pc87312.c
M hw/isa/piix.c
M hw/isa/vt82c686.c
M hw/m68k/mcf5206.c
M hw/m68k/mcf_intc.c
M hw/m68k/next-cube.c
M hw/m68k/next-kbd.c
M hw/mem/cxl_type3.c
M hw/misc/a9scu.c
M hw/misc/allwinner-cpucfg.c
M hw/misc/allwinner-h3-ccu.c
M hw/misc/allwinner-h3-dramc.c
M hw/misc/allwinner-h3-sysctrl.c
M hw/misc/allwinner-r40-ccu.c
M hw/misc/allwinner-r40-dramc.c
M hw/misc/allwinner-sid.c
M hw/misc/allwinner-sramc.c
M hw/misc/applesmc.c
M hw/misc/arm_l2x0.c
M hw/misc/arm_sysctl.c
M hw/misc/armsse-cpu-pwrctrl.c
M hw/misc/armsse-mhu.c
M hw/misc/aspeed_hace.c
M hw/misc/aspeed_i3c.c
M hw/misc/aspeed_lpc.c
M hw/misc/aspeed_peci.c
M hw/misc/aspeed_sbc.c
M hw/misc/aspeed_scu.c
M hw/misc/aspeed_sdmc.c
M hw/misc/aspeed_xdma.c
M hw/misc/avr_power.c
M hw/misc/bcm2835_cprman.c
M hw/misc/bcm2835_mbox.c
M hw/misc/bcm2835_mphi.c
M hw/misc/bcm2835_powermgt.c
M hw/misc/bcm2835_rng.c
M hw/misc/bcm2835_thermal.c
M hw/misc/eccmemctl.c
M hw/misc/exynos4210_clk.c
M hw/misc/exynos4210_pmu.c
M hw/misc/exynos4210_rng.c
M hw/misc/imx25_ccm.c
M hw/misc/imx31_ccm.c
M hw/misc/imx6_ccm.c
M hw/misc/imx6_src.c
M hw/misc/imx6ul_ccm.c
M hw/misc/imx7_ccm.c
M hw/misc/imx7_snvs.c
M hw/misc/imx7_src.c
M hw/misc/imx_rngc.c
M hw/misc/iotkit-secctl.c
M hw/misc/iotkit-sysctl.c
M hw/misc/ivshmem.c
M hw/misc/lasi.c
M hw/misc/led.c
M hw/misc/macio/cuda.c
M hw/misc/macio/gpio.c
M hw/misc/macio/mac_dbdma.c
M hw/misc/macio/pmu.c
M hw/misc/mips_cmgcr.c
M hw/misc/mips_cpc.c
M hw/misc/mips_itu.c
M hw/misc/mps2-fpgaio.c
M hw/misc/mps2-scc.c
M hw/misc/msf2-sysreg.c
M hw/misc/nrf51_rng.c
M hw/misc/pci-testdev.c
M hw/misc/sifive_e_aon.c
M hw/misc/sifive_u_prci.c
M hw/misc/slavio_misc.c
M hw/misc/stm32f2xx_syscfg.c
M hw/misc/stm32f4xx_exti.c
M hw/misc/stm32f4xx_syscfg.c
M hw/misc/tz-mpc.c
M hw/misc/tz-msc.c
M hw/misc/tz-ppc.c
M hw/misc/virt_ctrl.c
M hw/misc/xlnx-versal-cfu.c
M hw/net/allwinner-sun8i-emac.c
M hw/net/allwinner_emac.c
M hw/net/cadence_gem.c
M hw/net/can/can_kvaser_pci.c
M hw/net/can/can_mioe3680_pci.c
M hw/net/can/can_pcm3680_pci.c
M hw/net/can/ctucan_pci.c
M hw/net/can/xlnx-versal-canfd.c
M hw/net/dp8393x.c
M hw/net/etraxfs_eth.c
M hw/net/fsl_etsec/etsec.c
M hw/net/ftgmac100.c
M hw/net/imx_fec.c
M hw/net/lan9118.c
M hw/net/lance.c
M hw/net/lasi_i82596.c
M hw/net/mcf_fec.c
M hw/net/mipsnet.c
M hw/net/msf2-emac.c
M hw/net/npcm7xx_emc.c
M hw/net/npcm_gmac.c
M hw/net/opencores_eth.c
M hw/net/pcnet-pci.c
M hw/net/rocker/rocker.c
M hw/net/rtl8139.c
M hw/net/smc91c111.c
M hw/net/stellaris_enet.c
M hw/net/sungem.c
M hw/net/sunhme.c
M hw/net/tulip.c
M hw/net/vmxnet3.c
M hw/net/xilinx_axienet.c
M hw/net/xilinx_ethlite.c
M hw/nvme/ctrl.c
M hw/nvram/eeprom_at24c.c
M hw/nvram/fw_cfg.c
M hw/nvram/mac_nvram.c
M hw/nvram/nrf51_nvm.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_upstream.c
M hw/pci-bridge/i82801b11.c
M hw/pci-bridge/pci_bridge_dev.c
M hw/pci-bridge/pci_expander_bridge.c
M hw/pci-bridge/pcie_pci_bridge.c
M hw/pci-bridge/simba.c
M hw/pci-bridge/xio3130_downstream.c
M hw/pci-bridge/xio3130_upstream.c
M hw/pci-host/astro.c
M hw/pci-host/designware.c
M hw/pci-host/dino.c
M hw/pci-host/gt64120.c
M hw/pci-host/mv64361.c
M hw/pci-host/ppc440_pcix.c
M hw/pci-host/q35.c
M hw/pci-host/sabre.c
M hw/pci-host/versatile.c
M hw/pci-host/xilinx-pcie.c
M hw/ppc/pnv_psi.c
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/ppc4xx_sdram.c
M hw/ppc/ppce500_spin.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M hw/remote/proxy.c
M hw/rtc/allwinner-rtc.c
M hw/rtc/aspeed_rtc.c
M hw/rtc/ds1338.c
M hw/rtc/exynos4210_rtc.c
M hw/rtc/goldfish_rtc.c
M hw/rtc/ls7a_rtc.c
M hw/rtc/m48t59-isa.c
M hw/rtc/m48t59.c
M hw/rtc/xlnx-zynqmp-rtc.c
M hw/s390x/ccw-device.c
M hw/s390x/event-facility.c
M hw/s390x/ipl.c
M hw/s390x/s390-pci-bus.c
M hw/s390x/sclpquiesce.c
M hw/s390x/virtio-ccw.c
M hw/s390x/virtio-ccw.h
M hw/scsi/esp-pci.c
M hw/scsi/esp.c
M hw/scsi/lsi53c895a.c
M hw/scsi/megasas.c
M hw/scsi/mptsas.c
M hw/scsi/scsi-disk.c
M hw/scsi/scsi-generic.c
M hw/scsi/vmw_pvscsi.c
M hw/sd/allwinner-sdhost.c
M hw/sd/aspeed_sdhci.c
M hw/sd/bcm2835_sdhost.c
M hw/sd/cadence_sdhci.c
M hw/sd/npcm7xx_sdhci.c
M hw/sd/pl181.c
M hw/sd/pxa2xx_mmci.c
M hw/sd/sd.c
M hw/sd/sdhci.c
M hw/sd/ssi-sd.c
M hw/sensor/dps310.c
M hw/sensor/emc141x.c
M hw/sensor/lsm303dlhc_mag.c
M hw/sparc/sun4m_iommu.c
M hw/sparc64/sun4u_iommu.c
M hw/ssi/aspeed_smc.c
M hw/ssi/bcm2835_spi.c
M hw/ssi/ibex_spi_host.c
M hw/ssi/imx_spi.c
M hw/ssi/mss-spi.c
M hw/ssi/pl022.c
M hw/ssi/pnv_spi.c
M hw/ssi/sifive_spi.c
M hw/ssi/stm32f2xx_spi.c
M hw/ssi/xilinx_spi.c
M hw/ssi/xilinx_spips.c
M hw/ssi/xlnx-versal-ospi.c
M hw/timer/a9gtimer.c
M hw/timer/allwinner-a10-pit.c
M hw/timer/arm_mptimer.c
M hw/timer/armv7m_systick.c
M hw/timer/aspeed_timer.c
M hw/timer/avr_timer16.c
M hw/timer/bcm2835_systmr.c
M hw/timer/cmsdk-apb-dualtimer.c
M hw/timer/cmsdk-apb-timer.c
M hw/timer/digic-timer.c
M hw/timer/exynos4210_mct.c
M hw/timer/exynos4210_pwm.c
M hw/timer/grlib_gptimer.c
M hw/timer/hpet.c
M hw/timer/i8254.c
M hw/timer/ibex_timer.c
M hw/timer/imx_epit.c
M hw/timer/imx_gpt.c
M hw/timer/nrf51_timer.c
M hw/timer/renesas_cmt.c
M hw/timer/renesas_tmr.c
M hw/timer/sifive_pwm.c
M hw/timer/slavio_timer.c
M hw/timer/sse-counter.c
M hw/timer/sse-timer.c
M hw/timer/stm32f2xx_timer.c
M hw/tpm/tpm_tis_i2c.c
M hw/tpm/tpm_tis_isa.c
M hw/tpm/tpm_tis_sysbus.c
M hw/tricore/tricore_testdevice.c
M hw/usb/hcd-dwc3.c
M hw/usb/hcd-ehci-pci.c
M hw/usb/hcd-ehci-sysbus.c
M hw/usb/hcd-ohci-pci.c
M hw/usb/hcd-ohci-sysbus.c
M hw/usb/hcd-uhci.c
M hw/usb/hcd-xhci-pci.c
M hw/usb/hcd-xhci-sysbus.c
M hw/usb/hcd-xhci.c
M hw/usb/imx-usb-phy.c
M hw/usb/tusb6010.c
M hw/vfio/ap.c
M hw/vfio/ccw.c
M hw/vfio/pci.c
M hw/virtio/virtio-mmio.c
M hw/watchdog/cmsdk-apb-watchdog.c
M hw/watchdog/sbsa_gwdt.c
M hw/watchdog/wdt_aspeed.c
M hw/watchdog/wdt_diag288.c
M hw/watchdog/wdt_i6300esb.c
M hw/watchdog/wdt_ib700.c
M hw/watchdog/wdt_imx2.c
M include/hw/boards.h
M include/hw/qdev-core.h
M include/hw/resettable.h
M include/sysemu/hvf_int.h
M include/sysemu/kvm.h
M include/sysemu/kvm_int.h
A scripts/coccinelle/device-reset.cocci
M target/alpha/cpu.h
M target/arm/cpu-features.h
M target/arm/cpu64.c
M target/arm/hvf/hvf.c
M target/arm/hvf_arm.h
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/cpu64.c
M target/hppa/cpu.h
M target/i386/hvf/hvf.c
M target/i386/kvm/kvm.c
M target/s390x/cpu.c
M target/s390x/cpu.h
M target/s390x/sigp.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240913' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* s390: convert s390 virtio-ccw and CPU to three-phase reset
* reset: remove now-unused device_class_set_parent_reset()
* reset: introduce device_class_set_legacy_reset()
* reset: remove unneeded transitional machinery
* kvm: Use 'unsigned long' for request argument in functions wrapping ioctl()
* hvf: arm: Implement and use hvf_get_physical_address_range
so VMs can have larger-than-36-bit IPA spaces when the host
supports this
* target/arm/tcg: refine cache descriptions with a wrapper
* hw/net/can/xlnx-versal-canfd: fix various bugs
* MAINTAINERS: update versal, CAN maintainer entries
* hw/intc/arm_gic: fix spurious level triggered interrupts
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 13 Sep 2024 16:13:13 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240913' of
https://git.linaro.org/people/pmaydell/qemu-arm: (27 commits)
hw/intc/arm_gic: fix spurious level triggered interrupts
MAINTAINERS: Add my-self as CAN maintainer
MAINTAINERS: Update Xilinx Versal OSPI maintainer's email address
MAINTAINERS: Remove Vikram Garhwal as maintainer
hw/net/can/xlnx-versal-canfd: Fix FIFO issues
hw/net/can/xlnx-versal-canfd: Simplify DLC conversions
hw/net/can/xlnx-versal-canfd: Fix byte ordering
hw/net/can/xlnx-versal-canfd: Handle flags correctly
hw/net/can/xlnx-versal-canfd: Translate CAN ID registers
hw/net/can/xlnx-versal-canfd: Fix CAN FD flag check
hw/net/can/xlnx-versal-canfd: Fix interrupt level
target/arm/tcg: refine cache descriptions with a wrapper
hvf: arm: Implement and use hvf_get_physical_address_range
hvf: Split up hv_vm_create logic per arch
hw/boards: Add hvf_get_physical_address_range to MachineClass
kvm: Use 'unsigned long' for request argument in functions wrapping ioctl()
hw/core/resettable: Remove transitional_function machinery
hw/core/qdev: Simplify legacy_reset handling
hw: Remove device_phases_reset()
hw: Rename DeviceClass::reset field to legacy_reset
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/63731c346f07...28ae3179fc52
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