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[Qemu-commits] [qemu/qemu] fe678c: tcg: remove singlestep_enabled from D
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] fe678c: tcg: remove singlestep_enabled from DisasContextBase |
Date: |
Mon, 14 Oct 2024 05:03:19 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: fe678c45d2c970ab35826c6ff3ae08f20bf02f73
https://github.com/qemu/qemu/commit/fe678c45d2c970ab35826c6ff3ae08f20bf02f73
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M accel/tcg/translator.c
M include/exec/translator.h
M target/mips/tcg/translate.c
Log Message:
-----------
tcg: remove singlestep_enabled from DisasContextBase
It is used in a couple of places only, both within the same target.
Those can use the cflags just as well, so remove the separate field.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <20241010083641.1785069-1-pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f781af3b14fc87c5177d8d8e209d89743e4857df
https://github.com/qemu/qemu/commit/f781af3b14fc87c5177d8d8e209d89743e4857df
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M include/exec/cpu-common.h
M linux-user/elfload.c
Log Message:
-----------
include/exec: Introduce env_cpu_const()
It's the same as env_cpu(), but for const objects.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20240912093012.402366-2-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3674bfadb503e535250730be5df563f0d9928917
https://github.com/qemu/qemu/commit/3674bfadb503e535250730be5df563f0d9928917
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M linux-user/elfload.c
M linux-user/i386/cpu_loop.c
M linux-user/qemu.h
Log Message:
-----------
linux-user/i386: Emulate orig_ax
The kernel uses orig_rax/orig_eax to store the syscall number before
a syscall. One can see this value in core dumps and ptrace.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20240912093012.402366-3-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e7a4427aecfda9a73936966f356c59b988e68427
https://github.com/qemu/qemu/commit/e7a4427aecfda9a73936966f356c59b988e68427
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/i386/gdbstub.c
Log Message:
-----------
target/i386/gdbstub: Factor out gdb_get_reg() and gdb_write_reg()
i386 gdbstub handles both i386 and x86_64. Factor out two functions
for reading and writing registers without knowing their bitness.
While at it, simplify the TARGET_LONG_BITS == 32 case.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20240912093012.402366-4-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ac2fb86a0ed40095ddd1044e638fc36ee5295256
https://github.com/qemu/qemu/commit/ac2fb86a0ed40095ddd1044e638fc36ee5295256
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M configs/targets/i386-linux-user.mak
M configs/targets/x86_64-linux-user.mak
A gdb-xml/i386-32bit-linux.xml
A gdb-xml/i386-64bit-linux.xml
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/gdbstub.c
Log Message:
-----------
target/i386/gdbstub: Expose orig_ax
Copy XML files describing orig_ax from GDB and glue them with
CPUX86State.orig_ax.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20240912093012.402366-5-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9d08a70ddc08e9b6ecf870fd232531c78fe0b208
https://github.com/qemu/qemu/commit/9d08a70ddc08e9b6ecf870fd232531c78fe0b208
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M tests/tcg/multiarch/gdbstub/test-proc-mappings.py
Log Message:
-----------
tests/tcg: Run test-proc-mappings.py on i386
Now that orig_ax is exposed and GDB is happy, don't skip
test-proc-mappings.py on i386. In fact, it's broken only on
m68k now, so skip only this architecture.
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20240912093012.402366-6-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d0fb97402278c746ac89059e3dd57d2f59c1cc69
https://github.com/qemu/qemu/commit/d0fb97402278c746ac89059e3dd57d2f59c1cc69
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M linux-user/vm86.c
Log Message:
-----------
linux-user/vm86: Fix compilation with Clang
Since commit 95b9c27c81 ("linux-user: Remove unused handle_vm86_fault")
a bunch of other "static inline" function are now unused, too. Clang
warns about such unused "static inline" functions in .c files, so the
build currently breaks when compiling with "--enable-werror". Remove
the unused functions to get it going again.
Fixes: 95b9c27c81 ("linux-user: Remove unused handle_vm86_fault")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org>
Message-ID: <20241011161845.417342-1-thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 49d1866a6e53b84fd0aceced39ee3d01eb77e813
https://github.com/qemu/qemu/commit/49d1866a6e53b84fd0aceced39ee3d01eb77e813
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Assert noreturn from write-only page for atomics
There should be no "just in case"; the page is already
in the tlb, and known to be not readable.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: da335fe12a5da71a33d7afc2075a341f26213f53
https://github.com/qemu/qemu/commit/da335fe12a5da71a33d7afc2075a341f26213f53
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M include/exec/memop.h
M include/tcg/tcg.h
Log Message:
-----------
include/exec/memop: Move get_alignment_bits from tcg.h
This function is specific to MemOp, not TCG in general.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c5809eee452b0393ca57763137344099912b354a
https://github.com/qemu/qemu/commit/c5809eee452b0393ca57763137344099912b354a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
M include/exec/memop.h
M target/arm/tcg/translate-a64.c
M target/xtensa/translate.c
M tcg/arm/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg.c
Log Message:
-----------
include/exec/memop: Rename get_alignment_bits
Rename to use "memop_" prefix, like other functions
that operate on MemOp.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e5b063e81fd2b30aad1e9128238871c71b62a666
https://github.com/qemu/qemu/commit/e5b063e81fd2b30aad1e9128238871c71b62a666
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/memop.h
Log Message:
-----------
include/exec/memop: Introduce memop_atomicity_bits
Split out of mmu_lookup.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f168808d7d100ed96c52c4438c4ddb557bd086bf
https://github.com/qemu/qemu/commit/f168808d7d100ed96c52c4438c4ddb557bd086bf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M accel/tcg/cputlb.c
M include/hw/core/cpu.h
M include/hw/core/tcg-cpu-ops.h
M include/qemu/typedefs.h
Log Message:
-----------
accel/tcg: Add TCGCPUOps.tlb_fill_align
Add a new callback to handle softmmu paging. Return the page
details directly, instead of passing them indirectly to
tlb_set_page. Handle alignment simultaneously with paging so
that faults are handled with target-specific priority.
Route all calls of the two hooks through a tlb_fill_align
function local to cputlb.c.
As yet no targets implement the new hook.
As yet cputlb.c does not use the new alignment check.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 795592fef7d5d66a67b95a7f45cc1a84883db6a8
https://github.com/qemu/qemu/commit/795592fef7d5d66a67b95a7f45cc1a84883db6a8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Use the alignment test in tlb_fill_align
When we have a tlb miss, defer the alignment check to
the new tlb_fill_align hook. Move the existing alignment
check so that we only perform it with a tlb hit.
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4e6939c9344cd99059571c51457d7f024d1572de
https://github.com/qemu/qemu/commit/4e6939c9344cd99059571c51457d7f024d1572de
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/hppa/cpu.h
M target/hppa/int_helper.c
M target/hppa/mem_helper.c
M target/hppa/op_helper.c
Log Message:
-----------
target/hppa: Add MemOp argument to hppa_get_physical_address
Just add the argument, unused at this point.
Zero is the safe do-nothing value for all callers.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 32142b807726e56b422c6990454f5dca0ef8d80f
https://github.com/qemu/qemu/commit/32142b807726e56b422c6990454f5dca0ef8d80f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/hppa/mem_helper.c
Log Message:
-----------
target/hppa: Perform access rights before protection id check
In Chapter 5, Interruptions, the group 3 exceptions lists
"Data memory access rights trap" in priority order ahead of
"Data memory protection ID trap".
Swap these checks in hppa_get_physical_address.
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d73d4a5d78cabc55c837bc3303326659d8bc23a0
https://github.com/qemu/qemu/commit/d73d4a5d78cabc55c837bc3303326659d8bc23a0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/hppa/mem_helper.c
Log Message:
-----------
target/hppa: Fix priority of T, D, and B page faults
Drop the 'else' so that ret is overridden with the
highest priority fault.
Fixes: d8bc1381250 ("target/hppa: Implement PSW_X")
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5d29587b451b6b86738f62378f8e4fc98c22388f
https://github.com/qemu/qemu/commit/5d29587b451b6b86738f62378f8e4fc98c22388f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/hppa/mem_helper.c
Log Message:
-----------
target/hppa: Handle alignment faults in hppa_get_physical_address
In Chapter 5, Interruptions, the group 3 exceptions lists
"Unaligned data reference trap" has higher priority than
"Data memory break trap".
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 99746de61262fd5cf80eacfdb513e8d40e9107e8
https://github.com/qemu/qemu/commit/99746de61262fd5cf80eacfdb513e8d40e9107e8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/hppa/cpu.c
M target/hppa/cpu.h
M target/hppa/mem_helper.c
Log Message:
-----------
target/hppa: Implement TCGCPUOps.tlb_fill_align
Convert hppa_cpu_tlb_fill to hppa_cpu_tlb_fill_align so that we
can recognize alignment exceptions in the correct priority order.
Resolves: https://bugzilla.kernel.org/show_bug.cgi?id=219339
Tested-by: Helge Deller <deller@gmx.de>
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ec2c933701a438af478b03b904a2dbc9f1836941
https://github.com/qemu/qemu/commit/ec2c933701a438af478b03b904a2dbc9f1836941
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/m_helper.c
M target/arm/tcg/tlb_helper.c
Log Message:
-----------
target/arm: Pass MemOp to get_phys_addr
Zero is the safe do-nothing value for callers to use.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 29b4d7dbd21731fb974363f3d6b34d50f08fc24f
https://github.com/qemu/qemu/commit/29b4d7dbd21731fb974363f3d6b34d50f08fc24f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
Log Message:
-----------
target/arm: Pass MemOp to get_phys_addr_with_space_nogpc
Zero is the safe do-nothing value for callers to use.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5458670b15b9176dd75beb9516427ffb88e00a17
https://github.com/qemu/qemu/commit/5458670b15b9176dd75beb9516427ffb88e00a17
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Pass MemOp to get_phys_addr_gpc
Zero is the safe do-nothing value for callers to use.
Pass the value through from get_phys_addr.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c6cd9f9fa9fc62531ad0836401dac3feb4e73b30
https://github.com/qemu/qemu/commit/c6cd9f9fa9fc62531ad0836401dac3feb4e73b30
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Pass MemOp to get_phys_addr_nogpc
Zero is the safe do-nothing value for callers to use.
Pass the value through from get_phys_addr_gpc and
get_phys_addr_with_space_nogpc.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 21e5a2870e3c67ac903cde52c1c587a63d520d96
https://github.com/qemu/qemu/commit/21e5a2870e3c67ac903cde52c1c587a63d520d96
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Pass MemOp through get_phys_addr_twostage
Pass memop through get_phys_addr_twostage with its
recursion with get_phys_addr_nogpc.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c053f40b598e62e7c52665bb280d745d87954385
https://github.com/qemu/qemu/commit/c053f40b598e62e7c52665bb280d745d87954385
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Pass MemOp to get_phys_addr_lpae
Pass the value through from get_phys_addr_nogpc.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 64bda5106c56faa19a31e091aef3a08249cc4ad0
https://github.com/qemu/qemu/commit/64bda5106c56faa19a31e091aef3a08249cc4ad0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Move device detection earlier in get_phys_addr_lpae
Determine cache attributes, and thence Device vs Normal memory,
earlier in the function. We have an existing regime_is_stage2
if block into which this can be slotted.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1ba3cb88775fd7a9defae36855a99a2c64942905
https://github.com/qemu/qemu/commit/1ba3cb88775fd7a9defae36855a99a2c64942905
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/arm/cpu.c
M target/arm/internals.h
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/tlb_helper.c
Log Message:
-----------
target/arm: Implement TCGCPUOps.tlb_fill_align
Fill in the tlb_fill_align hook. Handle alignment not due to
memory type, since that's no longer handled by generic code.
Pass memop to get_phys_addr.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e530581ee06573fcf48c7f7a6c3f8ec6e5809243
https://github.com/qemu/qemu/commit/e530581ee06573fcf48c7f7a6c3f8ec6e5809243
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-10-13 (Sun, 13 Oct 2024)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Fix alignment fault priority in get_phys_addr_lpae
Now that we have the MemOp for the access, we can order
the alignment fault caused by memory type before the
permission fault for the page.
For subsequent page hits, permission and stage 2 checks
are known to pass, and so the TLB_CHECK_ALIGNED fault
raised in generic code is not mis-ordered.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3860a2a8de56fad71db42f4ad120eb7eff03b51f
https://github.com/qemu/qemu/commit/3860a2a8de56fad71db42f4ad120eb7eff03b51f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-10-14 (Mon, 14 Oct 2024)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/translator.c
M accel/tcg/user-exec.c
M configs/targets/i386-linux-user.mak
M configs/targets/x86_64-linux-user.mak
A gdb-xml/i386-32bit-linux.xml
A gdb-xml/i386-64bit-linux.xml
M include/exec/cpu-common.h
M include/exec/memop.h
M include/exec/translator.h
M include/hw/core/cpu.h
M include/hw/core/tcg-cpu-ops.h
M include/qemu/typedefs.h
M include/tcg/tcg.h
M linux-user/elfload.c
M linux-user/i386/cpu_loop.c
M linux-user/qemu.h
M linux-user/vm86.c
M target/arm/cpu.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/m_helper.c
M target/arm/tcg/tlb_helper.c
M target/arm/tcg/translate-a64.c
M target/hppa/cpu.c
M target/hppa/cpu.h
M target/hppa/int_helper.c
M target/hppa/mem_helper.c
M target/hppa/op_helper.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/gdbstub.c
M target/mips/tcg/translate.c
M target/xtensa/translate.c
M tcg/arm/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg.c
M tests/tcg/multiarch/gdbstub/test-proc-mappings.py
Log Message:
-----------
Merge tag 'pull-tcg-20241013' of https://gitlab.com/rth7680/qemu into staging
linux-user/i386: Emulate orig_ax
linux-user/vm86: Fix compilation with Clang
tcg: remove singlestep_enabled from DisasContextBase
accel/tcg: Add TCGCPUOps.tlb_fill_align
target/hppa: Handle alignment faults in hppa_get_physical_address
target/arm: Fix alignment fault priority in get_phys_addr_lpae
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# gpg: Signature made Sun 13 Oct 2024 23:10:22 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20241013' of https://gitlab.com/rth7680/qemu: (27 commits)
target/arm: Fix alignment fault priority in get_phys_addr_lpae
target/arm: Implement TCGCPUOps.tlb_fill_align
target/arm: Move device detection earlier in get_phys_addr_lpae
target/arm: Pass MemOp to get_phys_addr_lpae
target/arm: Pass MemOp through get_phys_addr_twostage
target/arm: Pass MemOp to get_phys_addr_nogpc
target/arm: Pass MemOp to get_phys_addr_gpc
target/arm: Pass MemOp to get_phys_addr_with_space_nogpc
target/arm: Pass MemOp to get_phys_addr
target/hppa: Implement TCGCPUOps.tlb_fill_align
target/hppa: Handle alignment faults in hppa_get_physical_address
target/hppa: Fix priority of T, D, and B page faults
target/hppa: Perform access rights before protection id check
target/hppa: Add MemOp argument to hppa_get_physical_address
accel/tcg: Use the alignment test in tlb_fill_align
accel/tcg: Add TCGCPUOps.tlb_fill_align
include/exec/memop: Introduce memop_atomicity_bits
include/exec/memop: Rename get_alignment_bits
include/exec/memop: Move get_alignment_bits from tcg.h
accel/tcg: Assert noreturn from write-only page for atomics
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/b38d263bca64...3860a2a8de56
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