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Re: [Qemu-devel] Missing ARMv6 instructions?

From: Kevin F. Quinn
Subject: Re: [Qemu-devel] Missing ARMv6 instructions?
Date: Sun, 2 Apr 2006 03:26:04 +0200

On Sat, 1 Apr 2006 23:06:07 +0300
Jonas Maebe <address@hidden> wrote:

> On 01 Apr 2006, at 22:51, Chris Wilson wrote:
> > and they have been an extensive user of software patents,
> And how:
>    http://www.patent.gov.uk/patent/legal/summaries/2004/o29204.htm
> "The invention in this case involves locating all of the input  
> registers in one data storage area, and all of the output registers  
> in another data storage area. Then the simulator only has to switch  
> the two storage areas around (eg. by exchanging two pointer values)  
> in order to effectively COPY all of the output registers to the  
> corresponding input registers of the next stage in a single  
> operation. The Hearing Officer concluded that this invention did  
> involve a technical contribution — not simply because it produced a  
> faster simulator, but because the fundamental construction of the  
> simulator had been modified."

I've got a better idea.  In an imaginary 3-stage pipeline, instead of

i1[*] -> <stage1> -> o1[*]
i2[*] -> <stage2> -> o2[*]
i3[*] -> <stage3> -> o3[*]
i2[*] = o1[*]
i3[*] = o2[*]
<commit o3[*]>

which the patent optimises to:

i1[*] -> <stage1> -> o1[*]
i2[*] -> <stage2> -> o2[*]
i3[*] -> <stage3> -> o3[*]
i2,o1 = o1,i2
i3,o2 = o2,i3
<commit o3[*]>

how about this:

o2i3[*] -> <stage3> -> o3[*]
o1i2[*] -> <stage2> -> o2i3[*]
i1[*] -> <stage1> -> o1i2[*]
<commit o3[*]>

which saves mucking around with pointers completely (requires the
stages are implemented sequentially not in pararllel, but since we're
talking about a software simulation that's likely to be the case).

Doesn't break the patent (well, the summary at least) and is a fraction
quicker :)

To be honest both optimisations are clearly obvious to anyone
sufficiently skilled in the field - maybe not so much to hardware
engineers who tend to think in parallel but certainly to software
engineers who tend to think in series.

> In fact, wouldn't surprise me if Qemu violates this patent.

Qemu doesn't simulate the pipeline as such as it emulates each
instruction completely before starting the next one.  Makes things much
simpler - if you don't simulate the pipeline, you don't have to
simulate flushing it etc :). The patent is talking about much deeper
simulation, probably for use in simulating the core in relation to
other components, or for use in accurate timing simulations.

Kevin F. Quinn

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