[Qemu-devel] qemu/target-sh4 op_helper.c translate.c

[Paul Brook]

CVSROOT:        /sources/qemu
Module name:    qemu
Changes by:     Paul Brook <pbrook>     06/06/17 20:04:26

Modified files:
        target-sh4     : op_helper.c translate.c 

Log message:
        Remove debug output.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/op_helper.c?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/translate.c?cvsroot=qemu&r1=1.4&r2=1.5

Patches:
Index: op_helper.c
===================================================================
RCS file: /sources/qemu/qemu/target-sh4/op_helper.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- op_helper.c 27 Apr 2006 21:00:31 -0000      1.1
+++ op_helper.c 17 Jun 2006 20:04:26 -0000      1.2
@@ -135,7 +135,7 @@
     uint32_t tmp0, tmp2;
     uint8_t old_q, tmp1 = 0xff;
 
-    printf("div1 T0=0x%08x T1=0x%08x M=%d Q=%d T=%d\n", T0, T1, M, Q, T);
+    //printf("div1 T0=0x%08x T1=0x%08x M=%d Q=%d T=%d\n", T0, T1, M, Q, T);
     old_q = Q;
     if ((0x80000000 & T1) != 0)
        SETQ;
@@ -234,7 +234,7 @@
        SETT;
     else
        CLRT;
-    printf("Output: T1=0x%08x M=%d Q=%d T=%d\n", T1, M, Q, T);
+    //printf("Output: T1=0x%08x M=%d Q=%d T=%d\n", T1, M, Q, T);
 }
 
 void helper_dmulsl_T0_T1()

Index: translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-sh4/translate.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- translate.c 17 Jun 2006 19:58:25 -0000      1.4
+++ translate.c 17 Jun 2006 20:04:26 -0000      1.5
@@ -247,7 +247,6 @@
 #endif
     switch (ctx->opcode) {
     case 0x0019:               /* div0u */
-       printf("div0u\n");
        gen_op_div0u();
        return;
     case 0x000b:               /* rts */
@@ -509,7 +508,6 @@
        gen_op_cmp_str_T0_T1();
        return;
     case 0x2007:               /* div0s Rm,Rn */
-       printf("div0s\n");
        gen_op_movl_rN_T0(REG(B7_4));
        gen_op_movl_rN_T1(REG(B11_8));
        gen_op_div0s_T0_T1();