Re: [Qemu-devel] [PATCH] MIPS instruction set configuration

[Thiemo Seufer]

Stefan Weil wrote:
> Hi all,
> 
> just for information about current projects for QEMU MIPS:
> 
> my machine is AR7 which includes a MIPS 4KEc core.
> This core supports the MIPS32R2 architecture and has no FPU.
> 
> As far as I know the MIPS architecture, most CPU features
> can be read from well defined bits and bytes in the CP0 registers.
> 
> These registers should be set by every machine definition in QEMU.
> 
> So the emulation (translator) code could get all information needed from
> the CP0 registers which are part of variable "env". There is no
> need to introduce new defines or variables to get endianess,
> instruction set, presence of FPU or internal timer, and other
> features.

This is mostly true for MIPS32 (and later) conforming CPUs. Earlier ones
(like the vr5400 Dirk is interested in) didn't announce all their
capabilities via config registers, and coprocessor CP0, where the
config registers reside, wasn't standardised.

> And if generic property bits are not enough:
> the processor identification is part of the CP0 registers, too.
> 
> Of course, one might mirror some features in extra variables for
> performance reasons.
> 
> What do you think of my proposal?

It only works for the more modern CPUs. I think we have to invert the
scheme, that is, keep the "master copy" of the configuration in an
opaque place, and feed the config registers from there.


Thiemo