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Re: [Qemu-devel] [Bug] MIPS code fails at branch instruction
From: |
Stefan Weil |
Subject: |
Re: [Qemu-devel] [Bug] MIPS code fails at branch instruction |
Date: |
Sat, 17 Mar 2007 12:37:49 +0100 |
User-agent: |
IceDove 1.5.0.10 (X11/20070307) |
So an emulation has several options:
1. Show undefined behaviour (this is what it does today).
2. Emulate the behaviour of existing CPUs as far as possible.
As different CPUs behave different, this must depend on the
current CPU.
3. Display an error message.
The current solution (1) is not good, because users get crashes
and don't know the reason, and experienced users spend a lot of
time with debugging (at least I did).
Solution (2) is needed to run existing binary code.
Solution (3) is the minimum I expect of an emulation like QEMU.
I prefer a mix of solutions (2) and (3): display a message and
try to emulate the original behaviour.
Do you agree, and would you accept patches which implement this?
Stefan
PS. Emulation of undefined instructions / undefined behaviour has
a long tradition. In the old Z80 and 8086 days, it was
something like a game to analyse and use them :-)
Thiemo Seufer schrieb:
> Stefan Weil wrote:
>> QEMU MIPS emulation fails with code using "illegal" commands
>> in the delay slot of a branch.
>>
>> I had an endless loop with QEMU running the firmware of a
>> MIPS based router.
>>
>> MIPS says: branches, jumps, ... instructions should not be
>> placed in the delay slot of a branch or jump.
>>
>> Nevertheless, some routers use this kind of code.
>
> The architecture spec defines this as undefined behaviour. Other
> implementations of MIPS CPUs show funny effects which are hard
> to explain without detailed knowledge of the microarchitecture.
>
>> I wrote a test program to examine the difference between emulation
>> and a real MIPS CPU (see appendices).
>
> I wouldn't be surprised if it starts to fail for some other combinations
> like a mix of branch and branch likely instructions.
>
> (The semantics of a branch delay slot are: The instruction in the delay
> slot is executed, then the branch is executed. Now, when the instruction
> in the delay slot is itself a branch, what will happen to its delay slot?)
>
>
> Thiemo
>
- [Qemu-devel] [Bug] MIPS code fails at branch instruction, Stefan Weil, 2007/03/16
- Re: [Qemu-devel] [Bug] MIPS code fails at branch instruction, Thiemo Seufer, 2007/03/16
- Re: [Qemu-devel] [Bug] MIPS code fails at branch instruction,
Stefan Weil <=
- Re: [Qemu-devel] [Bug] MIPS code fails at branch instruction, Thiemo Seufer, 2007/03/17
- Re: [Qemu-devel] [Bug] MIPS code fails at branch instruction, Stefan Weil, 2007/03/17
- Re: [Qemu-devel] [Bug] MIPS code fails at branch instruction, Paul Brook, 2007/03/17
- Re: [Qemu-devel] [Bug] [Patch] MIPS code fails at branch instruction, Stefan Weil, 2007/03/19
- Re: [Qemu-devel] [Bug] [Patch] MIPS code fails at branch instruction, Thiemo Seufer, 2007/03/19
- Re: [Qemu-devel] [Bug] [Patch] MIPS code fails at branch instruction, Thiemo Seufer, 2007/03/19
- Re: [Qemu-devel] [Bug] [Patch] MIPS code fails at branch instruction, Alexander Voropay, 2007/03/20
- Re: [Qemu-devel] [Bug] [Patch] MIPS code fails at branch instruction, Thiemo Seufer, 2007/03/20
- Re: [Qemu-devel] [Bug] [Patch] MIPS code fails at branch instruction, Stefan Weil, 2007/03/20
- Re: [Qemu-devel] [Bug] [Patch] MIPS code fails at branch instruction, Thiemo Seufer, 2007/03/24