[Qemu-devel] [PATCH][SPARC] RDASR and WRASR instructions on SPARCv8

[Aurelien Jarno]

Hi all,

The SPARCv8 RDASR and WRASR instructions currently generate an
illegal_instruction trap for rs1 != 0, whereas the SPARCv8 
manual explicitely says that an rs1 value of 1...14 in an RDASR
instruction produces undefined results, but does not cause an 
illegal_instruction trap. The same applies for WRASR.

The patch below fixes the current implementation by doing the
same thing as the microSPARC II CPU, ie reading the y register
in all cases for the RDASR instruction, and doing a NOP when
rs1 != 0 for the WRASR instruction.

Bye,
Aurelien


Index: target-sparc/translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/translate.c,v
retrieving revision 1.38
diff -u -d -p -r1.38 translate.c
--- target-sparc/translate.c    25 Mar 2007 07:55:52 -0000      1.38
+++ target-sparc/translate.c    31 Mar 2007 23:52:18 -0000
@@ -1130,11 +1130,14 @@ static void disas_sparc_insn(DisasContex
                 rs1 = GET_FIELD(insn, 13, 17);
                 switch(rs1) {
                 case 0: /* rdy */
+#ifndef TARGET_SPARC64
+                case 0x01 ... 0x0e: /* undefined in the SPARCv8 manual, rdy on 
the microSPARC II */
+                case 0x0f:          /* stbar in the SPARCv8 manual, rdy on the 
microSPARC II */
+                case 0x10 ... 0x1f: /* implementation-dependent in the SPARCv8 
manual, rdy on the microSPARC II */
+#endif
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
                     gen_movl_T0_reg(rd);
                     break;
-                case 15: /* stbar / V9 membar */
-                   break; /* no effect? */
 #ifdef TARGET_SPARC64
                case 0x2: /* V9 rdccr */
                     gen_op_rdccr();
@@ -1160,6 +1163,8 @@ static void disas_sparc_insn(DisasContex
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
                     gen_movl_T0_reg(rd);
                     break;
+               case 0xf: /* V9 membar */
+                    break; /* no effect */
                case 0x13: /* Graphics Status */
                     if (gen_trap_ifnofpu(dc))
                         goto jmp_insn;
@@ -1879,7 +1887,11 @@ static void disas_sparc_insn(DisasContex
                                gen_op_xor_T1_T0();
                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
                                 break;
-#ifdef TARGET_SPARC64
+#ifndef TARGET_SPARC64
+                           case 0x01 ... 0x0f: /* undefined in the SPARCv8 
manual, nop on the microSPARC II */
+                           case 0x10 ... 0x1f: /* implementation-dependent in 
the SPARCv8 manual, nop on the microSPARC II */
+                                break;
+#else
                            case 0x2: /* V9 wrccr */
                                 gen_op_wrccr();
                                break;

-- 
  .''`.  Aurelien Jarno             | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   address@hidden         | address@hidden
   `-    people.debian.org/~aurel32 | www.aurel32.net