[Qemu-devel] [PATCH] Arm MMU Fixes

[Matthew Warton]

Hi,

I recently tracked down a problem in the simulation of our software  
on Qemu to two small problems in the ARM MMU code.

The first is that Qemu would not enable changing of the pid register  
on processors with an MMU.  This is a legal operation, and one that  
several parts of our kernel rely on.  See (for example) the ARM920t  
technical reference manual to verify that this register is available  
on ARM processors with an MMU.

The second fix is more subtle.  The Qemu TLB is architecture  
independent, and therefore does not track Domains with TLB entries.   
Thus when the domain register is changed the TLB needs to be flushed  
so that all of the memory accesses are again checked with the new  
permissions.  The lack of this flush was causing a protection fault  
to not be delivered in certain circumstances, leading to incorrect  
software execution.

I would appreciate it if you could incorporate this patch into future  
releases of Qemu.

Thankyou,
Matthew Warton

Open Kernel Labs
www.ok-labs.com

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