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[Qemu-devel] Re: TCG on i386 can't generate qemu_st64 for 32-bit target

From: Fabrice Bellard
Subject: [Qemu-devel] Re: TCG on i386 can't generate qemu_st64 for 32-bit target
Date: Tue, 26 Feb 2008 23:05:47 +0100
User-agent: Thunderbird (X11/20070212)

Blue Swirl wrote:
> Hi,
> There is a problem with the Sparc32 target on i386 host. Store double
> word op (std) cannot be generated and TCG just aborts. It looks like
> the registers are so few on i386 that TCG can't find registers for the
> qemu_st64 call. The problem does not appear on x86_64 host, or for
> Sparc64 target (stx/ldx) on i386, or with 64-bit load (ldd) on Sparc32
> target.
> The attached patch would work around the problem, but I agree that
> it's ugly and it would bring back one instance of T2 use. I also tried
> preallocating a 64-bit register but that didn't help.
> I suppose instead the following piece (tcg/i386/tcg-target.c:737)
> could be modified to lower the pressure for registers but I'm not that
> familiar with x86 assembly.
> [...]

There are not enough free registers because of the legacy 3 cpu_T[n]
fixed registers. Once you have no helpers using cpu_T[n] implicitely, it
will be possible to allocate cpu_T[n] as normal temporaries and to free
the associated fixed registers.

Before that your solution is acceptable. Another hack would be to force
the 'r_dword' variable to be stored in cpu_T[1] and cpu_T[2], but TCG
gives no clean way to do it.


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