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Re: [Qemu-devel] [4239] x86/x86-64 MMU PAE fixes
From: |
Stuart Brady |
Subject: |
Re: [Qemu-devel] [4239] x86/x86-64 MMU PAE fixes |
Date: |
Tue, 22 Apr 2008 23:19:24 +0100 |
User-agent: |
Mutt/1.5.13 (2006-08-11) |
On Tue, Apr 22, 2008 at 09:57:12PM +0100, Paul Brook wrote:
> On Tuesday 22 April 2008, Aurelien Jarno wrote:
> > -#define PHYS_ADDR_MASK 0xfffff000
> > +#define PHYS_ADDR_MASK (~0xfff)
>
> I think this is wrong. According to my docs physical addresses have an
> architectural limit of 52 bits. Bits 52-62 of a PTE are reserved (must be
> zero), and bit 63 is the NX bit.
The documentation I'm using:
"Intel 64 and IA-32 Architectures Software Development Manual,
Volume 3A: System Programming Guide, Part 1"
"3.8 36-Bit Physical Addressing Using The PAE Paging Mechanism"
Lists bits 36-63 as "must be zero".
(For i386, or x86_64 running in 32-bit mode.)
"3.10 PAE-Enabled Paging in IA-32e Mode"
Lists bits 40-51 as "must be zero".
Lists bits 52 to 62 as "available".
Lists bit 63 as "EXB" (i.e. the NX bit).
(For x86_64 running in 64-bit mode.)
HTH,
--
Stuart Brady