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[Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 to TCG
From: |
Andreas Färber |
Subject: |
[Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 to TCG |
Date: |
Tue, 2 Sep 2008 18:57:20 +0200 |
Hello,
Attached patch replaces op_moven_T2_T0 with tcg_gen_not_{tl,i64}.
Signed-off-by: Andreas Faerber <address@hidden>
i64 was used for ppc64, so that I assume it is equivalent to tl. No
test setup to check.
Andreas
diff --git a/target-ppc/op.c b/target-ppc/op.c
index 3ee326d..e663e60 100644
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -136,13 +136,6 @@ void OPPROTO op_set_Rc0 (void)
RETURN();
}
-/* Constants load */
-void OPPROTO op_moven_T2_T0 (void)
-{
- T2 = ~T0;
- RETURN();
-}
-
/* Generate exceptions */
void OPPROTO op_raise_exception_err (void)
{
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index fe1de7e..9068936 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -914,7 +914,7 @@ GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03,
PPC_INTEGER);
/* subf subf. subfo subfo. */
static always_inline void gen_op_subfo (void)
{
- gen_op_moven_T2_T0();
+ tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
gen_op_subf();
gen_op_check_addo();
}
@@ -922,7 +922,7 @@ static always_inline void gen_op_subfo (void)
#define gen_op_subf_64 gen_op_subf
static always_inline void gen_op_subfo_64 (void)
{
- gen_op_moven_T2_T0();
+ tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
gen_op_subf();
gen_op_check_addo_64();
}
@@ -936,7 +936,7 @@ static always_inline void gen_op_subfc (void)
}
static always_inline void gen_op_subfco (void)
{
- gen_op_moven_T2_T0();
+ tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
gen_op_subf();
gen_op_check_subfc();
gen_op_check_addo();
@@ -949,7 +949,7 @@ static always_inline void gen_op_subfc_64 (void)
}
static always_inline void gen_op_subfco_64 (void)
{
- gen_op_moven_T2_T0();
+ tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
gen_op_subf();
gen_op_check_subfc_64();
gen_op_check_addo_64();
@@ -959,7 +959,7 @@ GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00,
PPC_INTEGER);
/* subfe subfe. subfeo subfeo. */
static always_inline void gen_op_subfeo (void)
{
- gen_op_moven_T2_T0();
+ tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
gen_op_subfe();
gen_op_check_addo();
}
@@ -967,7 +967,7 @@ static always_inline void gen_op_subfeo (void)
#define gen_op_subfe_64 gen_op_subfe
static always_inline void gen_op_subfeo_64 (void)
{
- gen_op_moven_T2_T0();
+ tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
gen_op_subfe_64();
gen_op_check_addo_64();
}
op_moven.diff
Description: Binary data
- [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} to TCG, Andreas Färber, 2008/09/02
- [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG, Andreas Färber, 2008/09/02
- [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 to TCG, Andreas Färber, 2008/09/02
- Re: [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 to TCG, Aurelien Jarno, 2008/09/02
- [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 to TCG,
Andreas Färber <=
- [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} to TCG, Andreas Färber, 2008/09/02
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} to TCG, Aurelien Jarno, 2008/09/02
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Andreas Färber, 2008/09/02
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Aurelien Jarno, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Andreas Färber, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Thiemo Seufer, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Andreas Färber, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Blue Swirl, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Andreas Färber, 2008/09/03
- Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG, Blue Swirl, 2008/09/03