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Re: [Qemu-devel] sparc y register
From: |
Blue Swirl |
Subject: |
Re: [Qemu-devel] sparc y register |
Date: |
Fri, 12 Sep 2008 19:28:17 +0300 |
On 9/12/08, Vince Weaver <address@hidden> wrote:
>
> On Thu, 11 Sep 2008, Blue Swirl wrote:
>
> > Thanks, I applied a fix based on this. There was also a similar
> > problem in mulscc, maybe your tests run better now?
> >
>
> So it turns out there are three problems:
> 1. mulscc when y has upper word bits set
> 2. mulscc when src1 has upper word bits set
> 3. mulscc when src2 has upper word bits set
>
> The patch from yesterday fixed case 1, but there were still problems for
> 2&3.
>
> Below is a patch I made that seems to get this all working properly. I've
> also attached a small test program that exhibits the 3 problems...
>
> I'm running the big Fortran program again, but it would take a few hours to
> finish if this is a proper fix so I thought I'd send this off now rather
> than waiting.
It's not proper to use i32 operations on i64 TCG registers. So I'd add
explicit masking operations.
With this patch applied, I get:
Test1: High bits in y : Pass
Test2: High bits in src : Pass
Test3: High bits in src2 : Pass
fix_mulscc_high_bits.diff
Description: plain/text