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Re: [Qemu-devel] Re: [PATCH 2/3] take3 sh4: Add IRL(4bit encoded interru


From: takasi-y
Subject: Re: [Qemu-devel] Re: [PATCH 2/3] take3 sh4: Add IRL(4bit encoded interrupt input) support.
Date: Fri, 31 Oct 2008 02:28:57 +0900 (JST)

Hi,

> If an irq is active at some level, and another irq at some other level
> arrives, doesn't the first one get lost? Maybe SH has edge-triggered
> irqs and this is OK, I don't know.
It is level, and is OK, though it is not clear if it really will lost not.
I guess it will be, because HW manual doesn't show a register to hold
pending state, and says not to alter the signal until it is processed.
But anyway, It wont be a problem. 
Because, AFAIK, they always have external HW to resend the unhandled irq.
Actually, the implementation is simply a priority encoder. But with irq
source holding request until software clears it, it works as resend.

> Sparc32 has similar 15 level interrupt system with priorities. I've
> used a separate qemu_irq for each of these, but perhaps your way could
> work if I used a bitmap.
I have tried 16 signals version too, because I thought it would be simpler.
But I found it is not only just moving of priority encoder from FPGA to CPU,
but also I have to add state variable to hold pending state.
And, IMHO, interfaces should not be changed from real HW. Or we will be
in trouble when generate emulation code using hardware description.
# I can't do it now. But it is what I would like to do...
/yoshii




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