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[Qemu-devel] [5596] target-ppc: be more consistent with temp variables n
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From: |
Aurelien Jarno |
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Subject: |
[Qemu-devel] [5596] target-ppc: be more consistent with temp variables naming |
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Date: |
Sun, 02 Nov 2008 08:22:34 +0000 |
Revision: 5596
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5596
Author: aurel32
Date: 2008-11-02 08:22:34 +0000 (Sun, 02 Nov 2008)
Log Message:
-----------
target-ppc: be more consistent with temp variables naming
Signed-off-by: Aurelien Jarno <address@hidden>
Modified Paths:
--------------
trunk/target-ppc/translate.c
Modified: trunk/target-ppc/translate.c
===================================================================
--- trunk/target-ppc/translate.c 2008-11-02 08:22:16 UTC (rev 5595)
+++ trunk/target-ppc/translate.c 2008-11-02 08:22:34 UTC (rev 5596)
@@ -832,15 +832,15 @@
int l1, l2;
uint32_t bi = rC(ctx->opcode);
uint32_t mask;
- TCGv temp;
+ TCGv t0;
l1 = gen_new_label();
l2 = gen_new_label();
mask = 1 << (3 - (bi & 0x03));
- temp = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
- tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
+ t0 = tcg_temp_new(TCG_TYPE_I32);
+ tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
if (rA(ctx->opcode) == 0)
tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
else
@@ -1953,22 +1953,22 @@
/* slw & slw. */
GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
{
- TCGv temp;
+ TCGv t0;
int l1, l2;
l1 = gen_new_label();
l2 = gen_new_label();
- temp = tcg_temp_local_new(TCG_TYPE_TL);
- tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);
- tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
+ t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
- tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
+ tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
+ tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
gen_set_label(l2);
- tcg_temp_free(temp);
+ tcg_temp_free(t0);
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
@@ -1986,22 +1986,22 @@
int sh = SH(ctx->opcode);
if (sh != 0) {
int l1, l2;
- TCGv temp;
+ TCGv t0;
l1 = gen_new_label();
l2 = gen_new_label();
- temp = tcg_temp_local_new(TCG_TYPE_TL);
- tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
- tcg_gen_brcondi_tl(TCG_COND_GE, temp, 0, l1);
- tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
- tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
+ t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
+ tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
+ tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
gen_set_label(l2);
- tcg_gen_ext32s_tl(temp, cpu_gpr[rS(ctx->opcode)]);
- tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], temp, sh);
- tcg_temp_free(temp);
+ tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
+ tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
+ tcg_temp_free(t0);
} else {
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
@@ -2012,24 +2012,24 @@
/* srw & srw. */
GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
{
- TCGv temp, temp2;
+ TCGv t0, t1;
int l1, l2;
l1 = gen_new_label();
l2 = gen_new_label();
- temp = tcg_temp_local_new(TCG_TYPE_TL);
- tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x20);
- tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
+ t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x3f);
- temp2 = tcg_temp_new(TCG_TYPE_TL);
- tcg_gen_ext32u_tl(temp2, cpu_gpr[rS(ctx->opcode)]);
- tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], temp2, temp);
- tcg_temp_free(temp2);
+ tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
+ t1 = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
+ tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
+ tcg_temp_free(t1);
gen_set_label(l2);
- tcg_temp_free(temp);
+ tcg_temp_free(t0);
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
@@ -2037,21 +2037,21 @@
/* sld & sld. */
GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
{
- TCGv temp;
+ TCGv t0;
int l1, l2;
l1 = gen_new_label();
l2 = gen_new_label();
- temp = tcg_temp_local_new(TCG_TYPE_TL);
- tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);
- tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
+ t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x40);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);
- tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
+ tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
+ tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
gen_set_label(l2);
- tcg_temp_free(temp);
+ tcg_temp_free(t0);
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
@@ -2069,13 +2069,13 @@
int sh = SH(ctx->opcode) + (n << 5);
if (sh != 0) {
int l1, l2;
- TCGv temp;
+ TCGv t0;
l1 = gen_new_label();
l2 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
- temp = tcg_temp_new(TCG_TYPE_TL);
- tcg_gen_andi_tl(temp, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
- tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
+ t0 = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
tcg_gen_br(l2);
gen_set_label(l1);
@@ -2100,21 +2100,21 @@
/* srd & srd. */
GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
{
- TCGv temp;
+ TCGv t0;
int l1, l2;
l1 = gen_new_label();
l2 = gen_new_label();
- temp = tcg_temp_local_new(TCG_TYPE_TL);
- tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x40);
- tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
+ t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x40);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_andi_tl(temp, cpu_gpr[rB(ctx->opcode)], 0x7f);
- tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], temp);
+ tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
+ tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
gen_set_label(l2);
- tcg_temp_free(temp);
+ tcg_temp_free(t0);
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
@@ -3652,30 +3652,30 @@
{ \
uint8_t bitmask; \
int sh; \
- TCGv temp1, temp2; \
+ TCGv t0, t1; \
sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
- temp1 = tcg_temp_new(TCG_TYPE_I32); \
+ t0 = tcg_temp_new(TCG_TYPE_I32); \
if (sh > 0) \
- tcg_gen_shri_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
+ tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
else if (sh < 0) \
- tcg_gen_shli_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
+ tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
else \
- tcg_gen_mov_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2]); \
- temp2 = tcg_temp_new(TCG_TYPE_I32); \
+ tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
+ t1 = tcg_temp_new(TCG_TYPE_I32); \
sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
if (sh > 0) \
- tcg_gen_shri_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
+ tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
else if (sh < 0) \
- tcg_gen_shli_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
+ tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
else \
- tcg_gen_mov_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2]); \
- tcg_op(temp1, temp1, temp2); \
+ tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
+ tcg_op(t0, t0, t1); \
bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
- tcg_gen_andi_i32(temp1, temp1, bitmask); \
- tcg_gen_andi_i32(temp2, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
- tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], temp1, temp2); \
- tcg_temp_free(temp1); \
- tcg_temp_free(temp2); \
+ tcg_gen_andi_i32(t0, t0, bitmask); \
+ tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
+ tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
+ tcg_temp_free(t0); \
+ tcg_temp_free(t1); \
}
/* crand */
@@ -3926,9 +3926,9 @@
tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
} else {
- TCGv temp = tcg_const_tl(crm);
- tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], temp);
- tcg_temp_free(temp);
+ TCGv t0 = tcg_const_tl(crm);
+ tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], t0);
+ tcg_temp_free(t0);
}
}
@@ -4040,10 +4040,10 @@
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
{
/* XXX: specification says this is treated as a load by the MMU */
- TCGv temp = tcg_temp_new(TCG_TYPE_TL);
- gen_addr_reg_index(temp, ctx);
- gen_qemu_ld8u(temp, temp, ctx->mem_idx);
- tcg_temp_free(temp);
+ TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
+ gen_addr_reg_index(t0, ctx);
+ gen_qemu_ld8u(t0, t0, ctx->mem_idx);
+ tcg_temp_free(t0);
}
/* dcbi (Supervisor only) */
@@ -4072,10 +4072,10 @@
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
{
/* XXX: specification say this is treated as a load by the MMU */
- TCGv temp = tcg_temp_new(TCG_TYPE_TL);
- gen_addr_reg_index(temp, ctx);
- gen_qemu_ld8u(temp, temp, ctx->mem_idx);
- tcg_temp_free(temp);
+ TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
+ gen_addr_reg_index(t0, ctx);
+ gen_qemu_ld8u(t0, t0, ctx->mem_idx);
+ tcg_temp_free(t0);
}
/* dcbt */
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