Re: [Qemu-devel] [PATCH] QEMU: Mask writes to RO bits in the command reg of PCI config space

[Aurelien Jarno]

On Tue, Dec 16, 2008 at 03:41:14PM +0000, Amit Shah wrote:
> The Command register in the PCI config space has some read-only bits.
> Any writes to those bits should be masked out.
> 
> Signed-off-by: Amit Shah <address@hidden>

Thanks applied.

> ---
>  qemu/hw/pci.c |    3 +++
>  qemu/hw/pci.h |    5 +++++
>  2 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/qemu/hw/pci.c b/qemu/hw/pci.c
> index f07892e..6ba8378 100644
> --- a/qemu/hw/pci.c
> +++ b/qemu/hw/pci.c
> @@ -452,6 +452,9 @@ void pci_default_write_config(PCIDevice *d,
>          if (can_write) {
>              /* Mask out writes to reserved bits in registers */
>              switch (addr) {
> +         case 0x05:
> +                val &= ~PCI_COMMAND_RESERVED_MASK_HI;
> +                break;
>              case 0x06:
>                  val &= ~PCI_STATUS_RESERVED_MASK_LO;
>                  break;
> diff --git a/qemu/hw/pci.h b/qemu/hw/pci.h
> index d25b0ca..35cc1e6 100644
> --- a/qemu/hw/pci.h
> +++ b/qemu/hw/pci.h
> @@ -61,6 +61,11 @@ typedef struct PCIIORegion {
>  
>  #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
>  
> +/* Bits in the PCI Command Register (PCI 2.3 spec) */
> +#define PCI_COMMAND_RESERVED 0xf800
> +
> +#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
> +
>  struct PCIDevice {
>      /* PCI config space */
>      uint8_t config[256];
> -- 
> 1.5.6.3
> 
> 
> 
> 

-- 
  .''`.  Aurelien Jarno             | GPG: 1024D/F1BCDB73
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