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Re: [Qemu-devel] [PATCH]: add leon target
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-devel] [PATCH]: add leon target |
Date: |
Thu, 8 Jan 2009 11:33:29 +0100 |
User-agent: |
Mutt/1.5.16 (2007-06-09) |
On Thu, Jan 08, 2009 at 11:09:45AM +0100, Tristan Gingold wrote:
>>>
>
> Hi,
>
>
>>> I have the same feeling too. I am ready to improve the code but I need a
>>> few advices.
>>> As currently implemented CPU emulation know about interrupt controller.
>>> Wether interrupt controller
>>> belongs to CPU or to the board is an open question :-)
>>> Do you simply prefer to have hooks in CPUSPARCState ?
>>
>> From my experience, interrupt controllers are usually not considered to
>> be part of the CPU.
>
> (What about LAPIC/LSAPIC ?)
There are ofcourse exceptions :)
>
>> Regarding the leon interrupt controller, I had a quick look at the vhdl
>> and
>> AFAICT there is no need for any special tricks in the sparc cpu model.
>> What you need is to handle accesses to the interrupt clear register, in
>> your
>> code you seem to call it ITC and your io_writel does not handle it.
>> This is the place to hook in calls to mask off bits from the pending
>> interrupt reg.
>>
>> Your leon software should be writing to this register when acking
>> interrupts.
>
> No. You have missed (p19):
>
> When the IU acknowledges the interrupt, the corresponding pending bit will
> automatically be cleared.
>
> This is the only reason why the CPU must inform the interrupt controller.
>
Not sure what docs you are refering to, but I had a second look at the
vhd and you seem to be correct. Odd...
Best regards