Re: [Qemu-devel] [PATCH 1/3] sh: SE7750 board definition

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:10 Sun 11 Jan     , Shin-ichiro KAWASAKI wrote:
> This patch simply provides basic SE7750 board definition.
> 
> 
> Signed-off-by: Shin-ichiro KAWASAKI <address@hidden>
> 
> Index: trunk/target-sh4/machine.c
> ===================================================================
> --- trunk/target-sh4/machine.c        (revision 6133)
> +++ trunk/target-sh4/machine.c        (working copy)
> @@ -5,4 +5,5 @@
>  {
>      qemu_register_machine(&shix_machine);
>      qemu_register_machine(&r2d_machine);
> +    qemu_register_machine(&se7750_machine);
>  }
> Index: trunk/target-sh4/translate.c
> ===================================================================
> --- trunk/target-sh4/translate.c      (revision 6133)
> +++ trunk/target-sh4/translate.c      (working copy)
> @@ -212,6 +212,12 @@
>  
>  static sh4_def_t sh4_defs[] = {
>      {
> +     .name = "SH7750",
> +     .id = SH_CPU_SH7750,
> +     .pvr = 0x04020500,
> +     .prr = 0x00000000,
> +     .cvr = 0x00000000,
> +    }, {
>       .name = "SH7750R",
>       .id = SH_CPU_SH7750R,
>       .pvr = 0x00050000,
> Index: trunk/Makefile.target
> ===================================================================
> --- trunk/Makefile.target     (revision 6133)
> +++ trunk/Makefile.target     (working copy)
> @@ -719,7 +719,7 @@
>  CPPFLAGS += -DHAS_AUDIO
>  endif
>  ifeq ($(TARGET_BASE_ARCH), sh4)
> -OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
> +OBJS+= shix.o r2d.o se.o sh7750.o sh7750_regnames.o tc58128.o
>  OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sh_pci.o sm501.o serial.o
>  OBJS+= ide.o
>  endif
> Index: trunk/hw/se.c
> ===================================================================
> --- trunk/hw/se.c     (revision 0)
> +++ trunk/hw/se.c     (revision 0)
> @@ -0,0 +1,94 @@
> +/*
> + * Hitachi ULSI Systems' evaludation boards, Solution Engine emulation.
> + *
> + * Copyright (c) 2008 Shin-ichiro KAWASAKI
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> + * of this software and associated documentation files (the "Software"), to 
> deal
> + * in the Software without restriction, including without limitation the 
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw.h"
> +#include "sh.h"
> +#include "sysemu.h"
> +#include "boards.h"
> +#include "sh7750_regs.h"
> +
> +#define SDRAM_BASE   0x0c000000 /* Physical location of SDRAM: Area 3 */
> +#define SDRAM_SIZE   0x02000000

> +#define ENTRY_OFFSET 0x00001000
> +#define COMMAND_LINE_OFFSET 0x0000100
IIRC it's the case for all SH4 maybe we could define it in a header and all
board to overwrite it
> +
> +static void se7750_init(ram_addr_t ram_size, int vga_ram_size,
> +                    const char *boot_device, DisplayState * ds,
> +                    const char *kernel_filename, const char *kernel_cmdline,
> +                    const char *initrd_filename, const char *cpu_model)
> +{
> +    CPUState *env;
> +    struct SH7750State *s;
> +    ram_addr_t sdram_addr;
> +    int kernel_size;
> +    uint8 * phys_load_addr = phys_ram_base;
> +
> +    /* initialize CPU */
> +    if (!cpu_model)
> +        cpu_model = "SH7750";
> +
> +    env = cpu_init(cpu_model);
> +    if (!env) {
> +        fprintf(stderr, "Unable to find CPU definition\n");
> +        exit(1);
> +    }
> +
> +    /* Allocate memory space */
> +    sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
> +    cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
> +
> +    /* Register peripherals */
> +    s = sh7750_init(env);
> +
> +    /* initialization which should be done by firmware */
> +    uint32_t bcr1 = 1 << 3; /* cs3 SDRAM */
> +    uint16_t bcr2 = 3 << (3 * 2); /* cs3 32-bit */
please move tihs too the beginning of the function

> +    cpu_physical_memory_write(SH7750_BCR1_A7, (uint8_t *)&bcr1, 4);
> +    cpu_physical_memory_write(SH7750_BCR2_A7, (uint8_t *)&bcr2, 2);
> +
> +    /* Start from P2 area */
> +    env->pc = SDRAM_BASE | 0xa0000000;
> +
> +    /* pass kernel cmdline */
> +    if (kernel_cmdline) {
> +        pstrcpy((char *)phys_load_addr + ENTRY_OFFSET + COMMAND_LINE_OFFSET,
> +                strlen(kernel_cmdline) + 1, kernel_cmdline);
> +        env->pc += 0x80000;
> +        phys_load_addr += 0x80000;
> +    }
do you known the flash model present on the real board?

Best Regards,
J.