[Qemu-devel] [PATCH] sh/serial: allow cpu regs definition

[Jean-Christophe PLAGNIOL-VILLARD]

sh_serial_regs will allow to define the SCI/SCIF cpu regs
need to add SH cpu other than sh7750

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <address@hidden>
---
apply after  sh: SCI improvements patch from Kawasaki-san

Best Regards,
J.
 hw/sh.h        |    2 +
 hw/sh7750.c    |   18 +++++++++++-
 hw/sh_serial.c |   86 ++++++++++++++++++++++++++-----------------------------
 hw/sh_serial.h |   41 ++++++++++++++++++++++++++
 4 files changed, 101 insertions(+), 46 deletions(-)
 create mode 100644 hw/sh_serial.h

diff --git a/hw/sh.h b/hw/sh.h
index 5e3c22b..c92fa8c 100644
--- a/hw/sh.h
+++ b/hw/sh.h
@@ -3,6 +3,7 @@
 /* Definitions for SH board emulation.  */
 
 #include "sh_intc.h"
+#include "sh_serial.h"
 
 #define A7ADDR(x) ((x) & 0x1fffffff)
 #define P4ADDR(x) ((x) | 0xe0000000)
@@ -38,6 +39,7 @@ void tmu012_init(target_phys_addr_t base, int feat, uint32_t 
freq,
 /* sh_serial.c */
 #define SH_SERIAL_FEAT_SCIF (1 << 0)
 void sh_serial_init (target_phys_addr_t base, int feat,
+                    sh_serial_regs *regs,
                     uint32_t freq, CharDriverState *chr,
                     qemu_irq eri_source,
                     qemu_irq rxi_source,
diff --git a/hw/sh7750.c b/hw/sh7750.c
index c8e3070..7b09ae8 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -30,6 +30,7 @@
 #include "sh7750_regs.h"
 #include "sh7750_regnames.h"
 #include "sh_intc.h"
+#include "sh_serial.h"
 #include "exec-all.h"
 #include "cpu.h"
 
@@ -714,6 +715,19 @@ static CPUWriteMemoryFunc *sh7750_mmct_write[] = {
     sh7750_mmct_writel
 };
 
+sh_serial_regs sh7750_sci = {
+    .scsmr = 0x0,
+    .scbrr = 0x4,
+    .scscr = 0x8,
+    .scfcr = 0x18,
+    .scfdr = 0x1c,
+    .scftdr = 0xc,
+    .scfsr = 0x10,
+    .scfrdr = 0x14,
+    .scsptr = 0x20,
+    .sclsr = 0x24,
+};
+
 SH7750State *sh7750_init(CPUSH4State * cpu)
 {
     SH7750State *s;
@@ -755,13 +769,15 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
 
     cpu->intc_handle = &s->intc;
 
-    sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
+    sh_serial_init(0x1fe00000, 0, &sh7750_sci,
+                  s->periph_freq, serial_hds[0],
                   s->intc.irqs[SCI1_ERI],
                   s->intc.irqs[SCI1_RXI],
                   s->intc.irqs[SCI1_TXI],
                   s->intc.irqs[SCI1_TEI],
                   NULL);
     sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
+                  &sh7750_sci,
                   s->periph_freq, serial_hds[1],
                   s->intc.irqs[SCIF_ERI],
                   s->intc.irqs[SCIF_RXI],
diff --git a/hw/sh_serial.c b/hw/sh_serial.c
index 3db7e6c..3d5870d 100644
--- a/hw/sh_serial.c
+++ b/hw/sh_serial.c
@@ -26,6 +26,7 @@
  */
 #include "hw.h"
 #include "sh.h"
+#include "sh_serial.h"
 #include "qemu-char.h"
 #include <assert.h>
 
@@ -65,6 +66,8 @@ typedef struct {
     qemu_irq txi;
     qemu_irq tei;
     qemu_irq bri;
+
+    sh_serial_regs *regs;
 } sh_serial_state;
 
 static void sh_serial_clear_fifo(sh_serial_state * s)
@@ -78,20 +81,22 @@ static void sh_serial_clear_fifo(sh_serial_state * s)
 static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
 {
     sh_serial_state *s = opaque;
+    sh_serial_regs *regs = s->regs;
     unsigned char ch;
 
 #ifdef DEBUG_SERIAL
     printf("sh_serial: write offs=0x%02x val=0x%02x\n",
           offs, val);
 #endif
-    switch(offs) {
-    case 0x00: /* SMR */
+    if (offs == regs->scsmr) { /* SMR */
         s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
         return;
-    case 0x04: /* BRR */
+    }
+    if (offs == regs->scbrr) { /* BRR */
         s->brr = val;
        return;
-    case 0x08: /* SCR */
+    }
+    if (offs == regs->scscr) { /* SCR */
         /* TODO : For SH7751, SCIF mask should be 0xfb. */
         s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
         if (!(val & (1 << 5)))
@@ -103,7 +108,8 @@ static void sh_serial_ioport_write(void *opaque, uint32_t 
offs, uint32_t val)
            qemu_set_irq(s->rxi, 0);
         }
         return;
-    case 0x0c: /* FTDR / TDR */
+    }
+    if (offs == regs->scftdr) { /* FTDR / TDR */
         if (s->chr) {
             ch = val;
             qemu_chr_write(s->chr, &ch, 1);
@@ -114,14 +120,13 @@ static void sh_serial_ioport_write(void *opaque, uint32_t 
offs, uint32_t val)
         else
             s->flags |= SH_SERIAL_FLAG_TDE;
         return;
-    case 0x14: /* FRDR / RDR */
+    }
+    if (offs == regs->scfrdr) { /* FRDR / RDR */
         /* do nothing */
         return;
-        break;
     }
     if (s->feat & SH_SERIAL_FEAT_SCIF) {
-        switch(offs) {
-        case 0x10: /* FSR */
+        if (offs == regs->scfsr) { /* FSR */
             if (!(val & (1 << 6)))
                 s->flags &= ~SH_SERIAL_FLAG_TEND;
             if (!(val & (1 << 5)))
@@ -139,7 +144,8 @@ static void sh_serial_ioport_write(void *opaque, uint32_t 
offs, uint32_t val)
                 }
             }
             return;
-        case 0x18: /* FCR */
+       }
+        if (offs == regs->scfcr) { /* FCR */
             s->fcr = val;
             switch ((val >> 6) & 3) {
             case 0:
@@ -161,15 +167,16 @@ static void sh_serial_ioport_write(void *opaque, uint32_t 
offs, uint32_t val)
             }
 
             return;
-        case 0x20: /* SPTR */
+       }
+        if (offs == regs->scsptr) { /* SPTR */
             s->sptr = val & 0xf3;
             return;
-        case 0x24: /* LSR */
+       }
+        if (offs == regs->sclsr) { /* LSR */
             return;
         }
     } else { /* SCI */
-        switch(offs) {
-        case 0x0c: /* TDR */
+        if (offs == regs->scftdr) { /* TDR */
             if (s->chr) {
                 ch = val;
                 qemu_chr_write(s->chr, &ch, 1);
@@ -180,7 +187,8 @@ static void sh_serial_ioport_write(void *opaque, uint32_t 
offs, uint32_t val)
                 qemu_set_irq(s->txi, 1);
             }
             return;
-        case 0x10: /* SSR */
+       }
+        if (offs == regs->scfsr) { /* SSR */
             /*
              * Ignore TDRE (1 << 7) bit because TDR is always
              * writable in this SCI emulation.
@@ -194,7 +202,8 @@ static void sh_serial_ioport_write(void *opaque, uint32_t 
offs, uint32_t val)
                 }
             }
             return;
-        case 0x1c:
+       }
+        if (offs == regs->scfdr) {
             s->sptr = val & 0x8f;
             return;
         }
@@ -207,22 +216,18 @@ static void sh_serial_ioport_write(void *opaque, uint32_t 
offs, uint32_t val)
 static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
 {
     sh_serial_state *s = opaque;
+    sh_serial_regs *regs = s->regs;
     uint32_t ret = ~0;
 
-    switch(offs) {
-    case 0x00: /* SMR */
+    if (offs == regs->scsmr) { /* SMR */
         ret = s->smr;
-        break;
-    case 0x04: /* BRR */
+    } else if (offs == regs->scbrr) { /* BRR */
         ret = s->brr;
-       break;
-    case 0x08: /* SCR */
+    } else if (offs == regs->scscr) { /* SCR */
         ret = s->scr;
-        break;
     }
     if (s->feat & SH_SERIAL_FEAT_SCIF) {
-        switch(offs) {
-        case 0x10: /* FSR */
+        if (offs == regs->scfsr) { /* FSR */
             ret = 0;
             if (s->flags & SH_SERIAL_FLAG_TEND)
                 ret |= (1 << 6);
@@ -238,8 +243,7 @@ static uint32_t sh_serial_ioport_read(void *opaque, 
uint32_t offs)
             if (s->scr & (1 << 5))
                 s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
 
-            break;
-        case 0x14:
+        } else if (offs == regs->scfrdr) {
             if (s->rx_cnt > 0) {
                 ret = s->rx_fifo[s->rx_tail++];
                 s->rx_cnt--;
@@ -248,26 +252,19 @@ static uint32_t sh_serial_ioport_read(void *opaque, 
uint32_t offs)
                 if (s->rx_cnt < s->rtrg)
                     s->flags &= ~SH_SERIAL_FLAG_RDF;
             }
-            break;
-        case 0x18:
+        } else if (offs == regs->scfcr) {
             ret = s->fcr;
-            break;
-        case 0x1c:
+        } else if (offs == regs->scfdr) {
             ret = s->rx_cnt;
-            break;
-        case 0x20:
+        } else if (offs == regs->scsptr) {
             ret = s->sptr;
-            break;
-        case 0x24:
+        } else if (offs == regs->sclsr) {
             ret = 0;
-            break;
         }
     } else {
-        switch(offs) {
-        case 0x0c: /* TDR */
+        if (offs == regs->scftdr) { /* TDR */
             ret = s->dr;
-            break;
-        case 0x10: /* SSR */
+        } else if (offs == regs->scfsr) { /* SSR */
             ret = 0;
             if (s->flags & SH_SERIAL_FLAG_TDE)
                 ret |= (1 << 7);
@@ -276,14 +273,11 @@ static uint32_t sh_serial_ioport_read(void *opaque, 
uint32_t offs)
             if (s->flags & SH_SERIAL_FLAG_TEND)
                 ret |= (1 << 2);
             /* TODO : handle bit MPBT */
-            break;
-        case 0x14: /* RDR */
+        } else if (offs == regs->scfrdr) { /* RDR */
             ret = s->rx_fifo[0];
             s->flags &= ~SH_SERIAL_FLAG_RDF;
-            break;
-        case 0x1c: /* SPTR */
+        } else if (offs == regs->scsptr) { /* SPTR */
             ret = s->sptr;
-            break;
         }
     }
 #ifdef DEBUG_SERIAL
@@ -379,6 +373,7 @@ static CPUWriteMemoryFunc *sh_serial_writefn[] = {
 };
 
 void sh_serial_init (target_phys_addr_t base, int feat,
+                    sh_serial_regs *regs,
                     uint32_t freq, CharDriverState *chr,
                     qemu_irq eri_source,
                     qemu_irq rxi_source,
@@ -394,6 +389,7 @@ void sh_serial_init (target_phys_addr_t base, int feat,
         return;
 
     s->feat = feat;
+    s->regs = regs;
     s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
     s->rtrg = 1;
 
diff --git a/hw/sh_serial.h b/hw/sh_serial.h
new file mode 100644
index 0000000..69345ac
--- /dev/null
+++ b/hw/sh_serial.h
@@ -0,0 +1,41 @@
+/*
+ * QEMU SH serial port emulation
+ *
+ * Copyright (c) 2009 Jean-Christophe PLAGNIOL-VILLARD <address@hidden>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __SH_SERIAL_H__
+#define __SH_SERIAL_H__
+
+typedef struct sh_serial_regs {
+    uint16_t scsmr;
+    uint16_t scbrr;
+    uint16_t scscr;
+    uint16_t scfcr;
+    uint16_t scfdr;
+    uint16_t scftdr;
+    uint16_t scfsr;
+    uint16_t scfrdr;
+    uint16_t scsptr;
+    uint16_t sclsr;
+} sh_serial_regs;
+
+#endif /* __SH_SERIAL_H__ */
-- 
1.5.6.5