Re: [Qemu-devel] SH: Improve the interrupt controller

[Vladimir Prus]

On Tuesday 17 February 2009 21:32:15 address@hidden wrote:
> Hi, Vladimir.
> 
> Some more fixes added. Would you please test this for your target?
> I would like you to post it if it works for yours.
> 
> I've tested 
>  Head: svn://svn.sv.gnu.org/qemu/address@hidden
>  + Last patch: 
> http://lists.gnu.org/archive/html/qemu-devel/2009-02/msg00546.html
>  + This patch.

Yoshii,

with these patches, I've got lockup again, so I've debugged deeper. The lockup 
happens
because the TMU0 source was asserted, but not enabled. On 7785, that source is 
controlled
using:

        - INT2PRI0 register, which is priority register. In debugger, I see 
write
        to this register being processed, and bumping enable_count.
        - INT2MSKR register (and it's clear register). It's never written.

On the CPU, INT2MSKR is initialized to all zeros, not masking anything. In QEMU,
we set enable_max to 2 and enable_count to 0. Therefore, after INT2PRI0 is 
written,
processor allows the interrupt, and QEMU does not. I attach a patch to correct
this -- what do you think?

Thanks,
Volodya


- Volodya

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