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[Qemu-devel] [PATCH 04/25] Fix bug: integer conditionnal branch offset i
From: |
Tristan Gingold |
Subject: |
[Qemu-devel] [PATCH 04/25] Fix bug: integer conditionnal branch offset is 21 bits wide. |
Date: |
Tue, 24 Mar 2009 16:47:46 +0100 |
Signed-off-by: Tristan Gingold <address@hidden>
---
target-alpha/translate.c | 20 ++++++++++----------
1 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 09065ac..dff3f1d 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -290,7 +290,7 @@ static always_inline void gen_store_mem (DisasContext *ctx,
static always_inline void gen_bcond (DisasContext *ctx,
TCGCond cond,
- int ra, int32_t disp16, int mask)
+ int ra, int32_t disp, int mask)
{
int l1, l2;
@@ -313,7 +313,7 @@ static always_inline void gen_bcond (DisasContext *ctx,
tcg_gen_movi_i64(cpu_pc, ctx->pc);
tcg_gen_br(l2);
gen_set_label(l1);
- tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
+ tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
gen_set_label(l2);
}
@@ -2285,42 +2285,42 @@ static always_inline int translate_one (DisasContext
*ctx, uint32_t insn)
break;
case 0x38:
/* BLBC */
- gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1);
+ gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);
ret = 1;
break;
case 0x39:
/* BEQ */
- gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0);
+ gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);
ret = 1;
break;
case 0x3A:
/* BLT */
- gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0);
+ gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);
ret = 1;
break;
case 0x3B:
/* BLE */
- gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0);
+ gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);
ret = 1;
break;
case 0x3C:
/* BLBS */
- gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1);
+ gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);
ret = 1;
break;
case 0x3D:
/* BNE */
- gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0);
+ gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);
ret = 1;
break;
case 0x3E:
/* BGE */
- gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0);
+ gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);
ret = 1;
break;
case 0x3F:
/* BGT */
- gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0);
+ gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);
ret = 1;
break;
invalid_opc:
--
1.6.2
- [Qemu-devel] [PATCH 0/25]: add alpha es40 system emulation (v3), Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 01/25] Add support for multi-level phys map., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 02/25] Fix bug: palcode is at least 6 bits., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 03/25] Fix bug: do not mask address LSBs for ldwu., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 04/25] Fix bug: integer conditionnal branch offset is 21 bits wide.,
Tristan Gingold <=
- [Qemu-devel] [PATCH 05/25] bug fix: avoid nop to override next instruction, Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 06/25] Fix temp free for hw_st, Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 07/25] Increase Alpha physical address size to 44 bits., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 08/25] Alpha: set target page size to 13 bits., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 09/25] Allow 5 mmu indexes., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 10/25] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 11/25] Add square wave output support., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 12/25] Add ali1543 super IO pci device., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 13/25] Add 21272 chipset (memory and pci controller for alpha), Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 14/25] Add target-alpha/machine.c and hw/es40.c for es40 machine emulation., Tristan Gingold, 2009/03/24