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Re: [Qemu-devel] [PATCH 1/4] move PPC insn flags to cpu.h
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From: |
Aurelien Jarno |
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Subject: |
Re: [Qemu-devel] [PATCH 1/4] move PPC insn flags to cpu.h |
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Date: |
Sat, 28 Mar 2009 23:58:05 +0100 |
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User-agent: |
Mutt/1.5.18 (2008-05-17) |
On Sat, Mar 28, 2009 at 02:30:14PM -0700, Nathan Froyd wrote:
> It makes more sense to put the flags in the header file than in the
> middle of translate.c.
If those definition are not used outside of translate.c, it makes no
sense to move them out to a header file included at multiple places.
OTOH, I agree that having them in the middle of translate.c is a bit
strange. Maybe we should move them at the top of the file along with
other definitions? In that case, GEN_HANDLER* and EXTRACT_HELPER are
also good candidates for the move.
> Signed-off-by: Nathan Froyd <address@hidden>
> ---
> target-ppc/cpu.h | 138
> ++++++++++++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 138
> ------------------------------------------------
> 2 files changed, 138 insertions(+), 138 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 87b3460..e11af60 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -283,6 +283,144 @@ enum powerpc_input_t {
> #define PPC_INPUT(env) (env->bus_model)
>
>
> /*****************************************************************************/
> +/* PowerPC Instructions types definitions
> */
> +enum {
> + PPC_NONE = 0x0000000000000000ULL,
> + /* PowerPC base instructions set
> */
> + PPC_INSNS_BASE = 0x0000000000000001ULL,
> + /* integer operations instructions
> */
> +#define PPC_INTEGER PPC_INSNS_BASE
> + /* flow control instructions
> */
> +#define PPC_FLOW PPC_INSNS_BASE
> + /* virtual memory instructions
> */
> +#define PPC_MEM PPC_INSNS_BASE
> + /* ld/st with reservation instructions
> */
> +#define PPC_RES PPC_INSNS_BASE
> + /* spr/msr access instructions
> */
> +#define PPC_MISC PPC_INSNS_BASE
> + /* Deprecated instruction sets
> */
> + /* Original POWER instruction set
> */
> + PPC_POWER = 0x0000000000000002ULL,
> + /* POWER2 instruction set extension
> */
> + PPC_POWER2 = 0x0000000000000004ULL,
> + /* Power RTC support
> */
> + PPC_POWER_RTC = 0x0000000000000008ULL,
> + /* Power-to-PowerPC bridge (601)
> */
> + PPC_POWER_BR = 0x0000000000000010ULL,
> + /* 64 bits PowerPC instruction set
> */
> + PPC_64B = 0x0000000000000020ULL,
> + /* New 64 bits extensions (PowerPC 2.0x)
> */
> + PPC_64BX = 0x0000000000000040ULL,
> + /* 64 bits hypervisor extensions
> */
> + PPC_64H = 0x0000000000000080ULL,
> + /* New wait instruction (PowerPC 2.0x)
> */
> + PPC_WAIT = 0x0000000000000100ULL,
> + /* Time base mftb instruction
> */
> + PPC_MFTB = 0x0000000000000200ULL,
> +
> + /* Fixed-point unit extensions
> */
> + /* PowerPC 602 specific
> */
> + PPC_602_SPEC = 0x0000000000000400ULL,
> + /* isel instruction
> */
> + PPC_ISEL = 0x0000000000000800ULL,
> + /* popcntb instruction
> */
> + PPC_POPCNTB = 0x0000000000001000ULL,
> + /* string load / store
> */
> + PPC_STRING = 0x0000000000002000ULL,
> +
> + /* Floating-point unit extensions
> */
> + /* Optional floating point instructions
> */
> + PPC_FLOAT = 0x0000000000010000ULL,
> + /* New floating-point extensions (PowerPC 2.0x)
> */
> + PPC_FLOAT_EXT = 0x0000000000020000ULL,
> + PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
> + PPC_FLOAT_FRES = 0x0000000000080000ULL,
> + PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
> + PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
> + PPC_FLOAT_FSEL = 0x0000000000400000ULL,
> + PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
> +
> + /* Vector/SIMD extensions
> */
> + /* Altivec support
> */
> + PPC_ALTIVEC = 0x0000000001000000ULL,
> + /* PowerPC 2.03 SPE extension
> */
> + PPC_SPE = 0x0000000002000000ULL,
> + /* PowerPC 2.03 SPE single-precision floating-point extension
> */
> + PPC_SPE_SINGLE = 0x0000000004000000ULL,
> + /* PowerPC 2.03 SPE double-precision floating-point extension
> */
> + PPC_SPE_DOUBLE = 0x0000000008000000ULL,
> +
> + /* Optional memory control instructions
> */
> + PPC_MEM_TLBIA = 0x0000000010000000ULL,
> + PPC_MEM_TLBIE = 0x0000000020000000ULL,
> + PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
> + /* sync instruction
> */
> + PPC_MEM_SYNC = 0x0000000080000000ULL,
> + /* eieio instruction
> */
> + PPC_MEM_EIEIO = 0x0000000100000000ULL,
> +
> + /* Cache control instructions
> */
> + PPC_CACHE = 0x0000000200000000ULL,
> + /* icbi instruction
> */
> + PPC_CACHE_ICBI = 0x0000000400000000ULL,
> + /* dcbz instruction with fixed cache line size
> */
> + PPC_CACHE_DCBZ = 0x0000000800000000ULL,
> + /* dcbz instruction with tunable cache line size
> */
> + PPC_CACHE_DCBZT = 0x0000001000000000ULL,
> + /* dcba instruction
> */
> + PPC_CACHE_DCBA = 0x0000002000000000ULL,
> + /* Freescale cache locking instructions
> */
> + PPC_CACHE_LOCK = 0x0000004000000000ULL,
> +
> + /* MMU related extensions
> */
> + /* external control instructions
> */
> + PPC_EXTERN = 0x0000010000000000ULL,
> + /* segment register access instructions
> */
> + PPC_SEGMENT = 0x0000020000000000ULL,
> + /* PowerPC 6xx TLB management instructions
> */
> + PPC_6xx_TLB = 0x0000040000000000ULL,
> + /* PowerPC 74xx TLB management instructions
> */
> + PPC_74xx_TLB = 0x0000080000000000ULL,
> + /* PowerPC 40x TLB management instructions
> */
> + PPC_40x_TLB = 0x0000100000000000ULL,
> + /* segment register access instructions for PowerPC 64 "bridge"
> */
> + PPC_SEGMENT_64B = 0x0000200000000000ULL,
> + /* SLB management
> */
> + PPC_SLBI = 0x0000400000000000ULL,
> +
> + /* Embedded PowerPC dedicated instructions
> */
> + PPC_WRTEE = 0x0001000000000000ULL,
> + /* PowerPC 40x exception model
> */
> + PPC_40x_EXCP = 0x0002000000000000ULL,
> + /* PowerPC 405 Mac instructions
> */
> + PPC_405_MAC = 0x0004000000000000ULL,
> + /* PowerPC 440 specific instructions
> */
> + PPC_440_SPEC = 0x0008000000000000ULL,
> + /* BookE (embedded) PowerPC specification
> */
> + PPC_BOOKE = 0x0010000000000000ULL,
> + /* mfapidi instruction
> */
> + PPC_MFAPIDI = 0x0020000000000000ULL,
> + /* tlbiva instruction
> */
> + PPC_TLBIVA = 0x0040000000000000ULL,
> + /* tlbivax instruction
> */
> + PPC_TLBIVAX = 0x0080000000000000ULL,
> + /* PowerPC 4xx dedicated instructions
> */
> + PPC_4xx_COMMON = 0x0100000000000000ULL,
> + /* PowerPC 40x ibct instructions
> */
> + PPC_40x_ICBT = 0x0200000000000000ULL,
> + /* rfmci is not implemented in all BookE PowerPC
> */
> + PPC_RFMCI = 0x0400000000000000ULL,
> + /* rfdi instruction
> */
> + PPC_RFDI = 0x0800000000000000ULL,
> + /* DCR accesses
> */
> + PPC_DCR = 0x1000000000000000ULL,
> + /* DCR extended accesse
> */
> + PPC_DCRX = 0x2000000000000000ULL,
> + /* user-mode DCR access, implemented in PowerPC 460
> */
> + PPC_DCRUX = 0x4000000000000000ULL,
> +};
> +
> +/*****************************************************************************/
> typedef struct ppc_def_t ppc_def_t;
> typedef struct opc_handler_t opc_handler_t;
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 952ee99..b89d42f 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -450,144 +450,6 @@ static always_inline target_ulong MASK (uint32_t start,
> uint32_t end)
> }
>
>
> /*****************************************************************************/
> -/* PowerPC Instructions types definitions
> */
> -enum {
> - PPC_NONE = 0x0000000000000000ULL,
> - /* PowerPC base instructions set
> */
> - PPC_INSNS_BASE = 0x0000000000000001ULL,
> - /* integer operations instructions
> */
> -#define PPC_INTEGER PPC_INSNS_BASE
> - /* flow control instructions
> */
> -#define PPC_FLOW PPC_INSNS_BASE
> - /* virtual memory instructions
> */
> -#define PPC_MEM PPC_INSNS_BASE
> - /* ld/st with reservation instructions
> */
> -#define PPC_RES PPC_INSNS_BASE
> - /* spr/msr access instructions
> */
> -#define PPC_MISC PPC_INSNS_BASE
> - /* Deprecated instruction sets
> */
> - /* Original POWER instruction set
> */
> - PPC_POWER = 0x0000000000000002ULL,
> - /* POWER2 instruction set extension
> */
> - PPC_POWER2 = 0x0000000000000004ULL,
> - /* Power RTC support
> */
> - PPC_POWER_RTC = 0x0000000000000008ULL,
> - /* Power-to-PowerPC bridge (601)
> */
> - PPC_POWER_BR = 0x0000000000000010ULL,
> - /* 64 bits PowerPC instruction set
> */
> - PPC_64B = 0x0000000000000020ULL,
> - /* New 64 bits extensions (PowerPC 2.0x)
> */
> - PPC_64BX = 0x0000000000000040ULL,
> - /* 64 bits hypervisor extensions
> */
> - PPC_64H = 0x0000000000000080ULL,
> - /* New wait instruction (PowerPC 2.0x)
> */
> - PPC_WAIT = 0x0000000000000100ULL,
> - /* Time base mftb instruction
> */
> - PPC_MFTB = 0x0000000000000200ULL,
> -
> - /* Fixed-point unit extensions
> */
> - /* PowerPC 602 specific
> */
> - PPC_602_SPEC = 0x0000000000000400ULL,
> - /* isel instruction
> */
> - PPC_ISEL = 0x0000000000000800ULL,
> - /* popcntb instruction
> */
> - PPC_POPCNTB = 0x0000000000001000ULL,
> - /* string load / store
> */
> - PPC_STRING = 0x0000000000002000ULL,
> -
> - /* Floating-point unit extensions
> */
> - /* Optional floating point instructions
> */
> - PPC_FLOAT = 0x0000000000010000ULL,
> - /* New floating-point extensions (PowerPC 2.0x)
> */
> - PPC_FLOAT_EXT = 0x0000000000020000ULL,
> - PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
> - PPC_FLOAT_FRES = 0x0000000000080000ULL,
> - PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
> - PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
> - PPC_FLOAT_FSEL = 0x0000000000400000ULL,
> - PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
> -
> - /* Vector/SIMD extensions
> */
> - /* Altivec support
> */
> - PPC_ALTIVEC = 0x0000000001000000ULL,
> - /* PowerPC 2.03 SPE extension
> */
> - PPC_SPE = 0x0000000002000000ULL,
> - /* PowerPC 2.03 SPE single-precision floating-point extension
> */
> - PPC_SPE_SINGLE = 0x0000000004000000ULL,
> - /* PowerPC 2.03 SPE double-precision floating-point extension
> */
> - PPC_SPE_DOUBLE = 0x0000000008000000ULL,
> -
> - /* Optional memory control instructions
> */
> - PPC_MEM_TLBIA = 0x0000000010000000ULL,
> - PPC_MEM_TLBIE = 0x0000000020000000ULL,
> - PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
> - /* sync instruction
> */
> - PPC_MEM_SYNC = 0x0000000080000000ULL,
> - /* eieio instruction
> */
> - PPC_MEM_EIEIO = 0x0000000100000000ULL,
> -
> - /* Cache control instructions
> */
> - PPC_CACHE = 0x0000000200000000ULL,
> - /* icbi instruction
> */
> - PPC_CACHE_ICBI = 0x0000000400000000ULL,
> - /* dcbz instruction with fixed cache line size
> */
> - PPC_CACHE_DCBZ = 0x0000000800000000ULL,
> - /* dcbz instruction with tunable cache line size
> */
> - PPC_CACHE_DCBZT = 0x0000001000000000ULL,
> - /* dcba instruction
> */
> - PPC_CACHE_DCBA = 0x0000002000000000ULL,
> - /* Freescale cache locking instructions
> */
> - PPC_CACHE_LOCK = 0x0000004000000000ULL,
> -
> - /* MMU related extensions
> */
> - /* external control instructions
> */
> - PPC_EXTERN = 0x0000010000000000ULL,
> - /* segment register access instructions
> */
> - PPC_SEGMENT = 0x0000020000000000ULL,
> - /* PowerPC 6xx TLB management instructions
> */
> - PPC_6xx_TLB = 0x0000040000000000ULL,
> - /* PowerPC 74xx TLB management instructions
> */
> - PPC_74xx_TLB = 0x0000080000000000ULL,
> - /* PowerPC 40x TLB management instructions
> */
> - PPC_40x_TLB = 0x0000100000000000ULL,
> - /* segment register access instructions for PowerPC 64 "bridge"
> */
> - PPC_SEGMENT_64B = 0x0000200000000000ULL,
> - /* SLB management
> */
> - PPC_SLBI = 0x0000400000000000ULL,
> -
> - /* Embedded PowerPC dedicated instructions
> */
> - PPC_WRTEE = 0x0001000000000000ULL,
> - /* PowerPC 40x exception model
> */
> - PPC_40x_EXCP = 0x0002000000000000ULL,
> - /* PowerPC 405 Mac instructions
> */
> - PPC_405_MAC = 0x0004000000000000ULL,
> - /* PowerPC 440 specific instructions
> */
> - PPC_440_SPEC = 0x0008000000000000ULL,
> - /* BookE (embedded) PowerPC specification
> */
> - PPC_BOOKE = 0x0010000000000000ULL,
> - /* mfapidi instruction
> */
> - PPC_MFAPIDI = 0x0020000000000000ULL,
> - /* tlbiva instruction
> */
> - PPC_TLBIVA = 0x0040000000000000ULL,
> - /* tlbivax instruction
> */
> - PPC_TLBIVAX = 0x0080000000000000ULL,
> - /* PowerPC 4xx dedicated instructions
> */
> - PPC_4xx_COMMON = 0x0100000000000000ULL,
> - /* PowerPC 40x ibct instructions
> */
> - PPC_40x_ICBT = 0x0200000000000000ULL,
> - /* rfmci is not implemented in all BookE PowerPC
> */
> - PPC_RFMCI = 0x0400000000000000ULL,
> - /* rfdi instruction
> */
> - PPC_RFDI = 0x0800000000000000ULL,
> - /* DCR accesses
> */
> - PPC_DCR = 0x1000000000000000ULL,
> - /* DCR extended accesse
> */
> - PPC_DCRX = 0x2000000000000000ULL,
> - /* user-mode DCR access, implemented in PowerPC 460
> */
> - PPC_DCRUX = 0x4000000000000000ULL,
> -};
> -
> -/*****************************************************************************/
> /* PowerPC instructions table
> */
> #if HOST_LONG_BITS == 64
> #define OPC_ALIGN 8
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net