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[Qemu-devel] Re: questions on default_config_write in hw/pci.c

From: Anthony Liguori
Subject: [Qemu-devel] Re: questions on default_config_write in hw/pci.c
Date: Thu, 30 Apr 2009 11:35:55 -0500
User-agent: Thunderbird (X11/20090320)

I can only answer some of this..

Michael S. Tsirkin wrote:
I've been looking at hw/pci.c, specifically at how config
read/write are implemented, and have a couple of questions
about default_config_write:

1. The code at the beginning (if len == 4 ...)
seems to only update pci base registers if a dword write is performed. I think it's legal for the guest to perform 4
   single-byte writes. Should this be supported?

2. The large switch statement at the end of this function
   uses hard-coded register offsets. Would it make sense
   to change it to use macros from hw/pci.h?


3. Still there I see:
        switch(d->config[0x0e]) {
        case 0x00:
        case 0x80:
   register 0x0e is header type, which has defined values
   of 0x00 (device or host bridge), 0x01 (pci to pci bridge) and
   0x02 (cardbus bridge). What is 0x80 and when is it used?
   Would it make sense to remove this?

4. Still there, there's some handling done for type 1 devices.
   This support seems imcomplete.
   Are there any PCI-to-PCI bridges emulated by qemu?
   Would it make sense to remove this code?

PCI-to-PCI bridges are used on non-x86 machine types by default. Presumably, they work enough for those boards. I've tried to use a PCI bridge in an x86 machine type but it's not very functional (IIRC, it didn't work for devices in any slot other than 0).


Anthony Liguori

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