[Qemu-devel] [PATCH 05/15] Peripheral driver for S3C SOC clock control.

[Vincent Sanders]

Signed-off-by: Vincent Sanders <address@hidden>
---
 Makefile.target     |    2 +-
 hw/s3c24xx_clkcon.c |  100 +++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 101 insertions(+), 1 deletions(-)
 create mode 100644 hw/s3c24xx_clkcon.c

diff --git a/Makefile.target b/Makefile.target
index 9d6d5fd..f5594fb 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -674,7 +674,7 @@ OBJS+= omap_sx1.o palm.o tsc210x.o
 OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
 OBJS+= mst_fpga.o mainstone.o
 OBJS+= musicpal.o pflash_cfi02.o
-OBJS+= s3c24xx_memc.o s3c24xx_irq.o
+OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o
 OBJS+= framebuffer.o
 CPPFLAGS += -DHAS_AUDIO
 endif
diff --git a/hw/s3c24xx_clkcon.c b/hw/s3c24xx_clkcon.c
new file mode 100644
index 0000000..bdae2c2
--- /dev/null
+++ b/hw/s3c24xx_clkcon.c
@@ -0,0 +1,100 @@
+/* hw/s3c24xx_clkcon.c
+ *
+ * Samsung S3C24XX Clock control emulation
+ *
+ * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+
+#include "s3c24xx.h"
+
+/* Lock time RW */
+#define S3C_REG_LOCKTIME 0
+
+/* MPLL Control RW */
+#define S3C_REG_MPLLCON 1
+
+/* UPLL Control RW */
+#define S3C_REG_UPLLCON 2
+
+/* Clock Generator Control RW */
+#define S3C_REG_CLKCON 3
+
+/* CLKCON IDLE */
+#define S3C_REG_CLKCON_IDLE (1<<2)
+
+/* Slow Clock Control RW */
+#define S3C_REG_CLKSLOW 4
+
+/* Clock divider control RW */
+#define S3C_REG_CLKDIVN 5
+
+static void
+s3c24xx_clkcon_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value)
+{
+    S3CState *soc = (S3CState *)opaque;
+    int addr = (addr_ & 0x1F) >> 2;
+    int idle_rising_edge = 0;
+
+    if (addr < 0 || addr > 5)
+        addr = 5;
+
+    if (addr == S3C_REG_CLKCON) {
+        if( !(soc->clkcon_reg[addr] & S3C_REG_CLKCON_IDLE) &&
+            (value & S3C_REG_CLKCON_IDLE) ) idle_rising_edge = 1;
+    }
+    soc->clkcon_reg[addr] = value;
+    if (idle_rising_edge) {
+        cpu_interrupt(soc->cpu_env, CPU_INTERRUPT_HALT);
+    }
+}
+
+static uint32_t
+s3c24xx_clkcon_read_f(void *opaque, target_phys_addr_t addr_)
+{
+    S3CState *soc = (S3CState *)opaque;
+    int addr = (addr_ & 0x1F) >> 2;
+
+    if (addr < 0 || addr > 5)
+        addr = 5;
+
+    return soc->clkcon_reg[addr];
+}
+
+static CPUReadMemoryFunc *s3c24xx_clkcon_read[] = {
+    &s3c24xx_clkcon_read_f,
+    &s3c24xx_clkcon_read_f,
+    &s3c24xx_clkcon_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_clkcon_write[] = {
+    &s3c24xx_clkcon_write_f,
+    &s3c24xx_clkcon_write_f,
+    &s3c24xx_clkcon_write_f,
+};
+
+
+void
+s3c24xx_clkcon_init(S3CState *soc, target_phys_addr_t base_addr)
+{
+    int tag;
+
+    tag = cpu_register_io_memory(0, s3c24xx_clkcon_read, s3c24xx_clkcon_write, 
soc);
+    cpu_register_physical_memory(base_addr, 6 * 4, tag);
+
+    /* initialise register values to power on defaults */
+    soc->clkcon_reg[S3C_REG_LOCKTIME] = 0x00FFFFFF;
+    soc->clkcon_reg[S3C_REG_MPLLCON] = 0x0005C080;
+    soc->clkcon_reg[S3C_REG_UPLLCON] = 0x00028080;
+    soc->clkcon_reg[S3C_REG_CLKCON] = 0x0007FFF0;
+    soc->clkcon_reg[S3C_REG_CLKSLOW] = 0x00000004;
+    soc->clkcon_reg[S3C_REG_CLKDIVN] = 0x00000000;
+
+    /* Currently it is assumed the t1 clock will be fed by a 12MHz source */
+    soc->tclk1 = 12000000;
+
+}
-- 
1.5.4.3