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[Qemu-devel] Re: target-sparc/TODO

From: Artyom Tarasenko
Subject: [Qemu-devel] Re: target-sparc/TODO
Date: Wed, 19 Aug 2009 12:17:17 +0200

2009/8/17 Blue Swirl <address@hidden>:
> On Mon, Aug 17, 2009 at 1:52 PM, Artyom
> Tarasenko<address@hidden> wrote:
>>> - Global register for regwptr, so that windowed registers can be
>>> accessed directly
>> looks like it's already implemented?
> No, this means that a global register (TCG_AREG1) would be designated
> as regwptr, so that the window registers (%o, %l, %i) would be defined
> with:
> cpu_wregs[i] = tcg_global_mem_new(TCG_AREG1, offsetof(...), name).
> This would need some changes to cwp handling to support TCG_AREG1,
> maybe also to TCG prologue.
> Before TCG, this was difficult because the registers were taken by
> cpu_T0, cpu_T1 and cpu_T2.
> But it's not clear if this gives any performance gain, because
> although window registers accesses may get faster (this is also not
> certain because CPUstate should reside in cache), there is one host
> register less available and that may mean more host memory accesses.

So, it's only about performance, otherwise the current implementation
is complete?

>>> - Synthetic instructions
>> Is it still open?
> We already handle 'clr' and 'mov'. Code generation is not optimal, for
> example arithmetic ops with constants/%g0 or things like wrpsr which
> always does a XOR of the parameters even if they are constants or %g0.

Would the synthetic ops with %g0 produce wrong results?
Particularly I'm interested if

jmp     %l1, %g4, %g0

may behave other than on a real hw.

>>> - Hardware breakpoint/watchpoint support
>> Is it still open?
> I think support for these was only found in a few CPU models, so they
> are not used much. Nobody has also shown any interest or provided a
> test case.

On OBP start-up I see some "write breakpoint reg" messages in the
debug log. Do they have to do with hardware breakpoint support?

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