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Re: [Qemu-devel] [PATCH v2 05/10] target-arm: optimize arm load/store mu


From: Juha.Riihimaki
Subject: Re: [Qemu-devel] [PATCH v2 05/10] target-arm: optimize arm load/store multiple ops
Date: Tue, 27 Oct 2009 09:48:46 +0100

On Oct 27, 2009, at 10:39, ext Aurelien Jarno wrote:

> On Sat, Oct 24, 2009 at 03:19:04PM +0300, address@hidden  
> wrote:
>> From: Juha Riihimäki <address@hidden>
>>
>> RM load/store multiple instructions can be slightly optimized by
>> loading the register offset constant into a variable outside the
>> register loop and using the preloaded variable inside the loop  
>> instead
>> of reloading the offset value to a temporary variable on each loop
>> iteration. This causes less TCG ops to be generated for a ARM load/
>> store multiple instruction if there are more than one register
>> accessed, otherwise the number of generated TCG ops is the same.
>>
>> Signed-off-by: Juha Riihimäki <address@hidden>
>> Acked-by: Laurent Desnogues <address@hidden>
>
> This patch breaks, the boot of an arm kernel, as tmp2 is used  
> elsewhere
> within this code path.

True, I just noticed that as well. This is because the resource leak  
patch
was refactored to utilize tmp2 inside the loop as well. I just sent a  
new
revision of this patch that uses tmp3 for th constant value.

> OTOH, while it reduce the number of TCG ops, that should not impact  
> the
> generated host asm code, as most (all ?) targets are able to add a
> small constant value to a register in one instruction.

This is true, but I still think it provides a small speed gain as  
there are
less TCG ops to be processed when generating host code...?


Cheers,
Juha



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