RE: [Qemu-devel] TBL register permissions for PPC

[Krumme, Chris]

________________________________

        From: address@hidden
[mailto:address@hidden On
Behalf Of Dima Ilyevsky
        Sent: Tuesday, December 01, 2009 12:33 PM
        To: address@hidden
        Subject: [Qemu-devel] TBL register permissions for PPC
        
        
        Hello All, 

        I have a question about read permissions of TBL SPR for all ppc
processors:
        I have discovered that my application, compiled by WindRiver
diab compiler and running in vxworks OS on ppc405 architecture bumps
into exception generated when trying to read TBL or TBU registers:


Hello Dmitry,

The code in question comes from hand coded area's so this is probably
not a compiler issue, now maybe there is an issue with the BSP, but that
is a different question.

Does the 405 manual indicate readability of that register?

Thanks

Chris



                program
                Exception current instruction address: 0x0003eb28
                Machine Status Register: 0x00088200
                Condition Register: 0x40000440

                <<<<<Registers>>>>>

                .....

                <<<<<Disassembly>>>>>

                 0x3eb08  4e800020    blr
                 0x3eb0c  3860ffff    li          r3,0xffff # -1
                 0x3eb10  4e800020    blr
                 0x3eb14  38a00000    li          r5,0x0 # 0
                 0x3eb18  7cbc43a6    mtspr       TBL,r5
                 0x3eb1c  7c7d43a6    mtspr       TBU,r3
                 0x3eb20  7c9c43a6    mtspr       TBL,r4
                 0x3eb24  4e800020    blr
                *0x3eb28  7cbd42a6    mfspr       r5,TBU
                 0x3eb2c  7cdc42a6    mfspr       r6,TBL
                 0x3eb30  7cfd42a6     mfspr       r7,TBU
                 0x3eb34  7c053800    cmp         crf0,0,r5,r7
                 0x3eb38  4082fff0       bc          0x4,2, 0x3eb28 #
vxTimeBaseGet
                 0x3eb3c  90a30000    stw         r5,0(r3)
                 0x3eb40  90c40000    stw         r6,0(r4)
                 0x3eb44  4e800020    blr

                <<<<<Traceback>>>>>
                ......


        I looked into qemu mfspr instruction implementation and
discovered that for some reason qemu had set NOACCESS permissions for
reading this register upon CPU initialization:


                /* Generic PowerPC time base */
                static void gen_tbl (CPUPPCState *env)
                {
                    spr_register(env, SPR_VTBL,  "TBL",
                                 &spr_read_tbl, SPR_NOACCESS,
                                 &spr_read_tbl, SPR_NOACCESS,
                                 0x00000000);
                    spr_register(env, SPR_TBL,   "TBL",
                                 SPR_NOACCESS, SPR_NOACCESS,
                                 SPR_NOACCESS, &spr_write_tbl,
                                 0x00000000);
                    spr_register(env, SPR_VTBU,  "TBU",
                                 &spr_read_tbu, SPR_NOACCESS,
                                 &spr_read_tbu, SPR_NOACCESS,
                                 0x00000000);
                    spr_register(env, SPR_TBU,   "TBU",
                                 SPR_NOACCESS, SPR_NOACCESS,
                                 SPR_NOACCESS, &spr_write_tbu,
                                 0x00000000);
                }


        Is this a right thing to do? it's certainly either qemu bug or
diab bug (which i don't think is likely, cause this code has been
running on the real hw without any issues)


        BR,
        Dmitry I.
        -- 
        
        
        Jonathan Swift
<http://www.brainyquote.com/quotes/authors/j/jonathan_swift.html>   -
"May you live every day of your life."