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[Qemu-devel] [PATCH 9/9] tcg: Allow target-specific implementation of NO
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 9/9] tcg: Allow target-specific implementation of NOR. |
Date: |
Fri, 19 Mar 2010 13:08:56 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/arm/tcg-target.h | 1 +
tcg/i386/tcg-target.h | 1 +
tcg/mips/tcg-target.h | 1 +
tcg/ppc/tcg-target.h | 1 +
tcg/ppc64/tcg-target.h | 2 ++
tcg/s390/tcg-target.h | 2 ++
tcg/sparc/tcg-target.h | 2 ++
tcg/tcg-op.h | 11 +++++++++++
tcg/tcg-opc.h | 6 ++++++
tcg/x86_64/tcg-target.h | 2 ++
10 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 0e8e1cc..c7bcc7f 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -69,6 +69,7 @@ enum {
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
+// #define TCG_TARGET_HAS_nor_i32
#define TCG_TARGET_HAS_GUEST_BASE
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 8e7ed11..d4fc348 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -59,6 +59,7 @@ enum {
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
+// #define TCG_TARGET_HAS_nor_i32
#define TCG_TARGET_HAS_GUEST_BASE
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 179151c..b65e085 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -89,6 +89,7 @@ enum {
#undef TCG_TARGET_HAS_orc_i32
#undef TCG_TARGET_HAS_eqv_i32
#undef TCG_TARGET_HAS_nand_i32
+#undef TCG_TARGET_HAS_nor_i32
/* optional instructions automatically implemented */
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 1087c00..a3c7093 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -91,6 +91,7 @@ enum {
#define TCG_TARGET_HAS_orc_i32
/* #define TCG_TARGET_HAS_eqv_i32 */
/* #define TCG_TARGET_HAS_nand_i32 */
+/* #define TCG_TARGET_HAS_nor_i32 */
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index acd1f57..4bf676b 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -82,6 +82,7 @@ enum {
/* #define TCG_TARGET_HAS_orc_i32 */
/* #define TCG_TARGET_HAS_eqv_i32 */
/* #define TCG_TARGET_HAS_nand_i32 */
+/* #define TCG_TARGET_HAS_nor_i32 */
#define TCG_TARGET_HAS_div_i64
/* #define TCG_TARGET_HAS_rot_i64 */
@@ -100,6 +101,7 @@ enum {
/* #define TCG_TARGET_HAS_orc_i64 */
/* #define TCG_TARGET_HAS_eqv_i64 */
/* #define TCG_TARGET_HAS_nand_i64 */
+/* #define TCG_TARGET_HAS_nor_i64 */
#define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index b0d2866..6fa4231 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -61,6 +61,7 @@ enum {
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
+// #define TCG_TARGET_HAS_nor_i32
// #define TCG_TARGET_HAS_div_i64
// #define TCG_TARGET_HAS_rot_i64
@@ -79,6 +80,7 @@ enum {
// #define TCG_TARGET_HAS_orc_i64
// #define TCG_TARGET_HAS_eqv_i64
// #define TCG_TARGET_HAS_nand_i64
+// #define TCG_TARGET_HAS_nor_i64
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_R15
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index b0b6c94..a4d1f36 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -102,6 +102,7 @@ enum {
#define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
+// #define TCG_TARGET_HAS_nor_i32
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_div_i64
@@ -121,6 +122,7 @@ enum {
#define TCG_TARGET_HAS_orc_i64
// #define TCG_TARGET_HAS_eqv_i64
// #define TCG_TARGET_HAS_nand_i64
+// #define TCG_TARGET_HAS_nor_i64
#endif
/* Note: must be synced with dyngen-exec.h and Makefile.target */
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 7bd498d..bafac2b 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1786,14 +1786,25 @@ static inline void tcg_gen_nand_i64(TCGv_i64 ret,
TCGv_i64 arg1, TCGv_i64 arg2)
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
+#ifdef TCG_TARGET_HAS_nor_i32
+ tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
+#else
tcg_gen_or_i32(ret, arg1, arg2);
tcg_gen_not_i32(ret, ret);
+#endif
}
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
+#ifdef TCG_TARGET_HAS_nor_i64
+ tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_nor_i32) && TCG_TARGET_REG_BITS == 32
+ tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+ tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
tcg_gen_or_i64(ret, arg1, arg2);
tcg_gen_not_i64(ret, ret);
+#endif
}
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 37ff0eb..5643d5d 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -120,6 +120,9 @@ DEF2(eqv_i32, 1, 2, 0, 0)
#ifdef TCG_TARGET_HAS_nand_i32
DEF2(nand_i32, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_nor_i32
+DEF2(nor_i32, 1, 2, 0, 0)
+#endif
#if TCG_TARGET_REG_BITS == 64
DEF2(mov_i64, 1, 1, 0, 0)
@@ -208,6 +211,9 @@ DEF2(eqv_i64, 1, 2, 0, 0)
#ifdef TCG_TARGET_HAS_nand_i64
DEF2(nand_i64, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_nor_i64
+DEF2(nor_i64, 1, 2, 0, 0)
+#endif
#endif
/* QEMU specific */
diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h
index 119b50a..223e667 100644
--- a/tcg/x86_64/tcg-target.h
+++ b/tcg/x86_64/tcg-target.h
@@ -88,6 +88,8 @@ enum {
// #define TCG_TARGET_HAS_eqv_i64
// #define TCG_TARGET_HAS_nand_i32
// #define TCG_TARGET_HAS_nand_i64
+// #define TCG_TARGET_HAS_nor_i32
+// #define TCG_TARGET_HAS_nor_i64
#define TCG_TARGET_HAS_GUEST_BASE
--
1.6.6.1
- [Qemu-devel] [PATCH 0/9] tcg cleanups, Richard Henderson, 2010/03/19
- [Qemu-devel] [PATCH 4/9] tcg: Change TCGType to an enumeration., Richard Henderson, 2010/03/19
- [Qemu-devel] [PATCH 3/9] tcg: Use TCGCond where appropriate., Richard Henderson, 2010/03/19
- [Qemu-devel] [PATCH 6/9] tcg: Use not_i32 to implement not_i64., Richard Henderson, 2010/03/19
- [Qemu-devel] [PATCH 7/9] tcg: Allow target-specific implementation of EQV., Richard Henderson, 2010/03/19
- [Qemu-devel] [PATCH 8/9] tcg: Allow target-specific implementation of NAND., Richard Henderson, 2010/03/19
- [Qemu-devel] [PATCH 5/9] tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs., Richard Henderson, 2010/03/19
- [Qemu-devel] [PATCH 1/9] tcg: Remove jmp opcode., Richard Henderson, 2010/03/19
- [Qemu-devel] [PATCH 9/9] tcg: Allow target-specific implementation of NOR.,
Richard Henderson <=
- [Qemu-devel] [PATCH 2/9] tcg: Name the opcode enumeration., Richard Henderson, 2010/03/19
- Re: [Qemu-devel] [PATCH 0/9] tcg cleanups, Aurelien Jarno, 2010/03/26