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[Qemu-devel] [PATCH v2 10/18] tcg/arm: add ext16u op
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v2 10/18] tcg/arm: add ext16u op |
Date: |
Sat, 10 Apr 2010 03:32:58 +0200 |
Add an ext16u op, either using the uxth instruction on ARMv6+ or two
shifts on previous ARM versions. In both cases the result use the same
number or less instructions than the pure TCG version.
Also move all sign extension code to separate functions, so that they
can be reused in other parts of the code.
Signed-off-by: Aurelien Jarno <address@hidden>
---
tcg/arm/tcg-target.c | 66 ++++++++++++++++++++++++++++++++++++-------------
tcg/arm/tcg-target.h | 4 +-
2 files changed, 50 insertions(+), 20 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index b9a6abd..1bff87d 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -485,6 +485,48 @@ static inline void tcg_out_smull32(TCGContext *s,
}
}
+static inline void tcg_out_ext8s(TCGContext *s, int cond,
+ int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* sxtb */
+ tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+ rd, 0, rn, SHIFT_IMM_LSL(24));
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+ rd, 0, rd, SHIFT_IMM_ASR(24));
+ }
+}
+
+static inline void tcg_out_ext16s(TCGContext *s, int cond,
+ int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* sxth */
+ tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+ rd, 0, rn, SHIFT_IMM_LSL(16));
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+ rd, 0, rd, SHIFT_IMM_ASR(16));
+ }
+}
+
+static inline void tcg_out_ext16u(TCGContext *s, int cond,
+ int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* uxth */
+ tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+ rd, 0, rn, SHIFT_IMM_LSL(16));
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+ rd, 0, rd, SHIFT_IMM_LSR(16));
+ }
+}
+
static inline void tcg_out_ld32_12(TCGContext *s, int cond,
int rd, int rn, tcg_target_long im)
{
@@ -1503,26 +1545,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
break;
case INDEX_op_ext8s_i32:
- if (use_armv6_instructions) {
- /* sxtb */
- tcg_out32(s, 0xe6af0070 | (args[0] << 12) | args[1]);
- } else {
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
- args[0], 0, args[1], SHIFT_IMM_LSL(24));
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
- args[0], 0, args[0], SHIFT_IMM_ASR(24));
- }
+ tcg_out_ext8s(s, COND_AL, args[0], args[1]);
break;
case INDEX_op_ext16s_i32:
- if (use_armv6_instructions) {
- /* sxth */
- tcg_out32(s, 0xe6bf0070 | (args[0] << 12) | args[1]);
- } else {
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
- args[0], 0, args[1], SHIFT_IMM_LSL(16));
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
- args[0], 0, args[0], SHIFT_IMM_ASR(16));
- }
+ tcg_out_ext16s(s, COND_AL, args[0], args[1]);
+ break;
+ case INDEX_op_ext16u_i32:
+ tcg_out_ext16u(s, COND_AL, args[0], args[1]);
break;
default:
@@ -1604,6 +1633,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_ext8s_i32, { "r", "r" } },
{ INDEX_op_ext16s_i32, { "r", "r" } },
+ { INDEX_op_ext16u_i32, { "r", "r" } },
{ -1 },
};
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index bc08f91..1f6d665 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -60,8 +60,8 @@ enum {
/* optional instructions */
#define TCG_TARGET_HAS_ext8s_i32
#define TCG_TARGET_HAS_ext16s_i32
-// #define TCG_TARGET_HAS_ext8u_i32
-// #define TCG_TARGET_HAS_ext16u_i32
+#undef TCG_TARGET_HAS_ext8u_i32 /* and r0, r1, #0xff */
+#define TCG_TARGET_HAS_ext16u_i32
// #define TCG_TARGET_HAS_bswap16_i32
// #define TCG_TARGET_HAS_bswap32_i32
#define TCG_TARGET_HAS_not_i32
--
1.7.0.4
- [Qemu-devel] [PATCH v2 0/18] tcg/arm: cleanup and improvements, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 05/18] tcg/arm: align 64-bit arguments in function calls, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 01/18] tcg/arm: remove SAVE_LR code, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 04/18] tcg/arm: replace integer values by registers enum, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 02/18] tcg/arm: explicitely list clobbered/reserved regs, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 07/18] tcg/arm: sxtb and sxth are available starting with ARMv6, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 03/18] tcg/arm: remove store signed functions, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 08/18] tcg/arm: use the blx instruction when possible, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 09/18] tcg/arm: add rotation ops, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 06/18] tcg/arm: add variables to define the allowed instructions set, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 10/18] tcg/arm: add ext16u op,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v2 11/18] tcg/arm: add bswap ops, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 12/18] tcg/arm: remove conditional argument for qemu_ld/st, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 16/18] tcg/arm: fix argument alignment in qemu_st64, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 18/18] tcg/arm: don't try to load constants using pc, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 17/18] tcg/arm: optimize register allocation order, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 13/18] tcg/arm: use ext* ops in qemu_ld, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 15/18] tcg/arm: remove useless register tests in qemu_ld/st, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 14/18] tcg/arm: bswap arguments in qemu_ld/st if needed, Aurelien Jarno, 2010/04/09