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[Qemu-devel] [PATCH] [MIPS] Correctly identify multiple cpus in SMP syst
From: |
Hervé Poussineau |
Subject: |
[Qemu-devel] [PATCH] [MIPS] Correctly identify multiple cpus in SMP systems |
Date: |
Sat, 31 Jul 2010 12:29:03 +0200 |
Signed-off-by: Hervé Poussineau <address@hidden>
---
target-mips/op_helper.c | 3 +--
target-mips/translate.c | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index a619b72..50c65bd 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1359,8 +1359,7 @@ void helper_mtc0_cause (target_ulong arg1)
void helper_mtc0_ebase (target_ulong arg1)
{
/* vectored interrupts not implemented */
- /* Multi-CPU not implemented */
- env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
+ env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
}
void helper_mtc0_config0 (target_ulong arg1)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 6c72dee..20b66a8 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12679,8 +12679,7 @@ void cpu_reset (CPUMIPSState *env)
env->CP0_Random = env->tlb->nb_tlb - 1;
env->tlb->tlb_in_use = env->tlb->nb_tlb;
env->CP0_Wired = 0;
- /* SMP not implemented */
- env->CP0_EBase = 0x80000000;
+ env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF);
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
/* vectored interrupts not implemented, timer on int 7,
no performance counters. */
--
1.7.1.GIT
- [Qemu-devel] [PATCH] [MIPS] Correctly identify multiple cpus in SMP systems,
Hervé Poussineau <=