Re: [Qemu-devel] [PATCH] target-ppc: clear MSR_POW on interrupt

[Alexander Graf]

Thomas Monjalon wrote:
> From: till <address@hidden>
>
> According to FreeScale's 'Programming Environments Manual for 32-bit
> Implementations of the PowerPC Architecture' [MPCFPE32B, Rev.3, 9/2005],
> section 6.5, table 6-7, an interrupt resets MSR_POW to zero but qemu-0.12.4
> fails to do so.
> Resetting the bit is necessary in order to bring the processor out of power
> management since otherwise it goes to sleep right away in the exception
> handler, i.e., it is impossible to leave PM-mode.
>   

This doesn't look right. POW shouldn't even get stored in SRR1. Could
you please redo the patch and make sure that mtmsr masks out MSR_POW?


Alex