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[Qemu-devel] [PATCH v2 10/20] x86: Properly reset PAT MSR
From: |
Jan Kiszka |
Subject: |
[Qemu-devel] [PATCH v2 10/20] x86: Properly reset PAT MSR |
Date: |
Tue, 15 Mar 2011 12:26:21 +0100 |
Conforming to the Intel spec, set the power-on value of PAT also on
reset, but save it across INIT.
Signed-off-by: Jan Kiszka <address@hidden>
---
target-i386/cpu.h | 4 ++--
target-i386/cpuid.c | 1 -
target-i386/helper.c | 5 +++++
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index d0eae75..c7047d5 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -685,8 +685,6 @@ typedef struct CPUX86State {
uint64_t tsc;
- uint64_t pat;
-
uint64_t mcg_status;
/* exception/interrupt handling */
@@ -707,6 +705,8 @@ typedef struct CPUX86State {
CPU_COMMON
+ uint64_t pat;
+
/* processor features (e.g. for CPUID insn) */
uint32_t cpuid_level;
uint32_t cpuid_vendor1;
diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c
index 5382a28..814d13e 100644
--- a/target-i386/cpuid.c
+++ b/target-i386/cpuid.c
@@ -847,7 +847,6 @@ int cpu_x86_register (CPUX86State *env, const char
*cpu_model)
env->cpuid_version |= ((def->model & 0xf) << 4) | ((def->model >> 4) <<
16);
env->cpuid_version |= def->stepping;
env->cpuid_features = def->features;
- env->pat = 0x0007040600070406ULL;
env->cpuid_ext_features = def->ext_features;
env->cpuid_ext2_features = def->ext2_features;
env->cpuid_ext3_features = def->ext3_features;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index a08309f..d15fca5 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -99,6 +99,8 @@ void cpu_reset(CPUX86State *env)
env->mxcsr = 0x1f80;
+ env->pat = 0x0007040600070406ULL;
+
memset(env->dr, 0, sizeof(env->dr));
env->dr[6] = DR6_FIXED_1;
env->dr[7] = DR7_FIXED_1;
@@ -1280,8 +1282,11 @@ CPUX86State *cpu_x86_init(const char *cpu_model)
void do_cpu_init(CPUState *env)
{
int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI;
+ uint64_t pat = env->pat;
+
cpu_reset(env);
env->interrupt_request = sipi;
+ env->pat = pat;
apic_init_reset(env->apic_state);
env->halted = !cpu_is_bsp(env);
}
--
1.7.1
[Qemu-devel] [PATCH v2 08/20] kvm: x86: Do not leave halt if interrupts are disabled, Jan Kiszka, 2011/03/15
[Qemu-devel] [PATCH v2 10/20] x86: Properly reset PAT MSR,
Jan Kiszka <=
[Qemu-devel] [PATCH v2 07/20] kvm: Add in-kernel irqchip awareness to cpu_thread_is_idle, Jan Kiszka, 2011/03/15
[Qemu-devel] [PATCH v2 12/20] kvm: x86: Synchronize PAT MSR with the kernel, Jan Kiszka, 2011/03/15
[Qemu-devel] [PATCH v2 03/20] s390: Detect invalid invocations of qemu_ram_free/remap, Jan Kiszka, 2011/03/15
[Qemu-devel] [PATCH v2 02/20] x86: Unbreak TCG support for hardware breakpoints, Jan Kiszka, 2011/03/15
[Qemu-devel] [PATCH v2 05/20] Redirect cpu_interrupt to callback handler, Jan Kiszka, 2011/03/15
[Qemu-devel] [PATCH v2 04/20] Break up user and system cpu_interrupt implementations, Jan Kiszka, 2011/03/15
[Qemu-devel] [PATCH v2 09/20] kvm: Mark VCPU state dirty on creation, Jan Kiszka, 2011/03/15
[Qemu-devel] [PATCH v2 16/20] kvm: Rework inner loop of kvm_cpu_exec, Jan Kiszka, 2011/03/15
[Qemu-devel] [PATCH v2 11/20] x86: Save/restore PAT MSR, Jan Kiszka, 2011/03/15
[Qemu-devel] [PATCH v2 20/20] Expose thread_id in info cpus, Jan Kiszka, 2011/03/15