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[Qemu-devel] Re: [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into
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From: |
Blue Swirl |
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Subject: |
[Qemu-devel] Re: [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs |
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Date: |
Mon, 28 Mar 2011 20:31:23 +0300 |
On Mon, Mar 28, 2011 at 4:44 PM, Peter Maydell <address@hidden> wrote:
> Combine the per-machine QEMUMachine struct into the per-machine
> sun4*_hwdef struct. This requires some moving around of init functions
> to avoid forward references. We also have to move the 'const'
> attribute from the whole sun4*_hwdef[] array to the individual fields
> of the structure, because QEMUMachine is not const.
Maybe QEMUMachine should be made const instead? The data does not ever
need to change.
> The motivation is to allow the init functions to get at the
> QEMUMachine struct for the board, so we can use its max_ram field
> rather than having a max_mem field in the sun4*_hwdef struct.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> hw/sun4m.c | 596
> ++++++++++++++++++++++++++++++------------------------------
> 1 files changed, 297 insertions(+), 299 deletions(-)
>
> diff --git a/hw/sun4m.c b/hw/sun4m.c
> index df3aa32..db90fbe 100644
> --- a/hw/sun4m.c
> +++ b/hw/sun4m.c
> @@ -87,51 +87,55 @@
> #define ESCC_CLOCK 4915200
>
> struct sun4m_hwdef {
> - target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len,
> slavio_base;
> - target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
> - target_phys_addr_t serial_base, fd_base;
> - target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
> - target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
> - target_phys_addr_t bpp_base, dbri_base, sx_base;
> - struct {
> + QEMUMachine machine;
> + const target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len;
> + const target_phys_addr_t slavio_base;
> + const target_phys_addr_t intctl_base, counter_base, nvram_base,
> ms_kb_base;
> + const target_phys_addr_t serial_base, fd_base;
> + const target_phys_addr_t afx_base, idreg_base, dma_base, esp_base,
> le_base;
> + const target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base,
> aux2_base;
> + const target_phys_addr_t bpp_base, dbri_base, sx_base;
> + const struct {
> target_phys_addr_t reg_base, vram_base;
> } vsimm[MAX_VSIMMS];
> - target_phys_addr_t ecc_base;
> - uint32_t ecc_version;
> - uint8_t nvram_machine_id;
> - uint16_t machine_id;
> - uint32_t iommu_version;
> - uint64_t max_mem;
> + const target_phys_addr_t ecc_base;
> + const uint32_t ecc_version;
> + const uint8_t nvram_machine_id;
> + const uint16_t machine_id;
> + const uint32_t iommu_version;
> + const uint64_t max_mem;
> const char * const default_cpu_model;
> };
>
> #define MAX_IOUNITS 5
>
> struct sun4d_hwdef {
> - target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
> - target_phys_addr_t counter_base, nvram_base, ms_kb_base;
> - target_phys_addr_t serial_base;
> - target_phys_addr_t espdma_base, esp_base;
> - target_phys_addr_t ledma_base, le_base;
> - target_phys_addr_t tcx_base;
> - target_phys_addr_t sbi_base;
> - uint8_t nvram_machine_id;
> - uint16_t machine_id;
> - uint32_t iounit_version;
> - uint64_t max_mem;
> + QEMUMachine machine;
> + const target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
> + const target_phys_addr_t counter_base, nvram_base, ms_kb_base;
> + const target_phys_addr_t serial_base;
> + const target_phys_addr_t espdma_base, esp_base;
> + const target_phys_addr_t ledma_base, le_base;
> + const target_phys_addr_t tcx_base;
> + const target_phys_addr_t sbi_base;
> + const uint8_t nvram_machine_id;
> + const uint16_t machine_id;
> + const uint32_t iounit_version;
> + const uint64_t max_mem;
> const char * const default_cpu_model;
> };
>
> struct sun4c_hwdef {
> - target_phys_addr_t iommu_base, slavio_base;
> - target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
> - target_phys_addr_t serial_base, fd_base;
> - target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
> - target_phys_addr_t tcx_base, aux1_base;
> - uint8_t nvram_machine_id;
> - uint16_t machine_id;
> - uint32_t iommu_version;
> - uint64_t max_mem;
> + QEMUMachine machine;
> + const target_phys_addr_t iommu_base, slavio_base;
> + const target_phys_addr_t intctl_base, counter_base, nvram_base,
> ms_kb_base;
> + const target_phys_addr_t serial_base, fd_base;
> + const target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
> + const target_phys_addr_t tcx_base, aux1_base;
> + const uint8_t nvram_machine_id;
> + const uint16_t machine_id;
> + const uint32_t iommu_version;
> + const uint64_t max_mem;
> const char * const default_cpu_model;
> };
>
> @@ -1006,9 +1010,109 @@ enum {
> ss2000_id,
> };
>
> -static const struct sun4m_hwdef sun4m_hwdefs[] = {
> +static struct sun4m_hwdef sun4m_hwdefs[];
> +
> +/* SPARCstation 5 hardware initialisation */
> +static void ss5_init(ram_addr_t RAM_size,
> + const char *boot_device,
> + const char *kernel_filename, const char *kernel_cmdline,
> + const char *initrd_filename, const char *cpu_model)
> +{
> + sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
> + kernel_cmdline, initrd_filename, cpu_model);
> +}
> +
> +/* SPARCstation 10 hardware initialisation */
> +static void ss10_init(ram_addr_t RAM_size,
> + const char *boot_device,
> + const char *kernel_filename, const char
> *kernel_cmdline,
> + const char *initrd_filename, const char *cpu_model)
> +{
> + sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
> + kernel_cmdline, initrd_filename, cpu_model);
> +}
> +
> +/* SPARCserver 600MP hardware initialisation */
> +static void ss600mp_init(ram_addr_t RAM_size,
> + const char *boot_device,
> + const char *kernel_filename,
> + const char *kernel_cmdline,
> + const char *initrd_filename, const char *cpu_model)
> +{
> + sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
> + kernel_cmdline, initrd_filename, cpu_model);
> +}
> +
> +/* SPARCstation 20 hardware initialisation */
> +static void ss20_init(ram_addr_t RAM_size,
> + const char *boot_device,
> + const char *kernel_filename, const char
> *kernel_cmdline,
> + const char *initrd_filename, const char *cpu_model)
> +{
> + sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
> + kernel_cmdline, initrd_filename, cpu_model);
> +}
> +
> +/* SPARCstation Voyager hardware initialisation */
> +static void vger_init(ram_addr_t RAM_size,
> + const char *boot_device,
> + const char *kernel_filename, const char
> *kernel_cmdline,
> + const char *initrd_filename, const char *cpu_model)
> +{
> + sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
> + kernel_cmdline, initrd_filename, cpu_model);
> +}
> +
> +/* SPARCstation LX hardware initialisation */
> +static void ss_lx_init(ram_addr_t RAM_size,
> + const char *boot_device,
> + const char *kernel_filename, const char
> *kernel_cmdline,
> + const char *initrd_filename, const char *cpu_model)
> +{
> + sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
> + kernel_cmdline, initrd_filename, cpu_model);
> +}
> +
> +/* SPARCstation 4 hardware initialisation */
> +static void ss4_init(ram_addr_t RAM_size,
> + const char *boot_device,
> + const char *kernel_filename, const char *kernel_cmdline,
> + const char *initrd_filename, const char *cpu_model)
> +{
> + sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
> + kernel_cmdline, initrd_filename, cpu_model);
> +}
> +
> +/* SPARCClassic hardware initialisation */
> +static void scls_init(ram_addr_t RAM_size,
> + const char *boot_device,
> + const char *kernel_filename, const char
> *kernel_cmdline,
> + const char *initrd_filename, const char *cpu_model)
> +{
> + sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
> + kernel_cmdline, initrd_filename, cpu_model);
> +}
> +
> +/* SPARCbook hardware initialisation */
> +static void sbook_init(ram_addr_t RAM_size,
> + const char *boot_device,
> + const char *kernel_filename, const char
> *kernel_cmdline,
> + const char *initrd_filename, const char *cpu_model)
> +{
> + sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
> + kernel_cmdline, initrd_filename, cpu_model);
> +}
> +
> +static struct sun4m_hwdef sun4m_hwdefs[] = {
> /* SS-5 */
> {
> + .machine = {
> + .name = "SS-5",
> + .desc = "Sun4m platform, SPARCstation 5",
> + .init = ss5_init,
> + .use_scsi = 1,
> + .is_default = 1,
> + },
> .iommu_base = 0x10000000,
> .iommu_pad_base = 0x10004000,
> .iommu_pad_len = 0x0fffb000,
> @@ -1037,6 +1141,13 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
> },
> /* SS-10 */
> {
> + .machine = {
> + .name = "SS-10",
> + .desc = "Sun4m platform, SPARCstation 10",
> + .init = ss10_init,
> + .use_scsi = 1,
> + .max_cpus = 4,
> + },
> .iommu_base = 0xfe0000000ULL,
> .tcx_base = 0xe20000000ULL,
> .slavio_base = 0xff0000000ULL,
> @@ -1063,6 +1174,13 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
> },
> /* SS-600MP */
> {
> + .machine = {
> + .name = "SS-600MP",
> + .desc = "Sun4m platform, SPARCserver 600MP",
> + .init = ss600mp_init,
> + .use_scsi = 1,
> + .max_cpus = 4,
> + },
> .iommu_base = 0xfe0000000ULL,
> .tcx_base = 0xe20000000ULL,
> .slavio_base = 0xff0000000ULL,
> @@ -1087,6 +1205,13 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
> },
> /* SS-20 */
> {
> + .machine = {
> + .name = "SS-20",
> + .desc = "Sun4m platform, SPARCstation 20",
> + .init = ss20_init,
> + .use_scsi = 1,
> + .max_cpus = 4,
> + },
> .iommu_base = 0xfe0000000ULL,
> .tcx_base = 0xe20000000ULL,
> .slavio_base = 0xff0000000ULL,
> @@ -1129,6 +1254,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
> },
> /* Voyager */
> {
> + .machine = {
> + .name = "Voyager",
> + .desc = "Sun4m platform, SPARCstation Voyager",
> + .init = vger_init,
> + .use_scsi = 1,
> + },
> .iommu_base = 0x10000000,
> .tcx_base = 0x50000000,
> .slavio_base = 0x70000000,
> @@ -1153,6 +1284,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
> },
> /* LX */
> {
> + .machine = {
> + .name = "LX",
> + .desc = "Sun4m platform, SPARCstation LX",
> + .init = ss_lx_init,
> + .use_scsi = 1,
> + },
> .iommu_base = 0x10000000,
> .iommu_pad_base = 0x10004000,
> .iommu_pad_len = 0x0fffb000,
> @@ -1178,6 +1315,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
> },
> /* SS-4 */
> {
> + .machine = {
> + .name = "SS-4",
> + .desc = "Sun4m platform, SPARCstation 4",
> + .init = ss4_init,
> + .use_scsi = 1,
> + },
> .iommu_base = 0x10000000,
> .tcx_base = 0x50000000,
> .cs_base = 0x6c000000,
> @@ -1203,6 +1346,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
> },
> /* SPARCClassic */
> {
> + .machine = {
> + .name = "SPARCClassic",
> + .desc = "Sun4m platform, SPARCClassic",
> + .init = scls_init,
> + .use_scsi = 1,
> + },
> .iommu_base = 0x10000000,
> .tcx_base = 0x50000000,
> .slavio_base = 0x70000000,
> @@ -1227,6 +1376,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
> },
> /* SPARCbook */
> {
> + .machine = {
> + .name = "SPARCbook",
> + .desc = "Sun4m platform, SPARCbook",
> + .init = sbook_init,
> + .use_scsi = 1,
> + },
> .iommu_base = 0x10000000,
> .tcx_base = 0x50000000, // XXX
> .slavio_base = 0x70000000,
> @@ -1251,219 +1406,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
> },
> };
>
> -/* SPARCstation 5 hardware initialisation */
> -static void ss5_init(ram_addr_t RAM_size,
> - const char *boot_device,
> - const char *kernel_filename, const char *kernel_cmdline,
> - const char *initrd_filename, const char *cpu_model)
> -{
> - sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
> - kernel_cmdline, initrd_filename, cpu_model);
> -}
> -
> -/* SPARCstation 10 hardware initialisation */
> -static void ss10_init(ram_addr_t RAM_size,
> - const char *boot_device,
> - const char *kernel_filename, const char
> *kernel_cmdline,
> - const char *initrd_filename, const char *cpu_model)
> -{
> - sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
> - kernel_cmdline, initrd_filename, cpu_model);
> -}
> -
> -/* SPARCserver 600MP hardware initialisation */
> -static void ss600mp_init(ram_addr_t RAM_size,
> - const char *boot_device,
> - const char *kernel_filename,
> - const char *kernel_cmdline,
> - const char *initrd_filename, const char *cpu_model)
> -{
> - sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
> - kernel_cmdline, initrd_filename, cpu_model);
> -}
> -
> -/* SPARCstation 20 hardware initialisation */
> -static void ss20_init(ram_addr_t RAM_size,
> - const char *boot_device,
> - const char *kernel_filename, const char
> *kernel_cmdline,
> - const char *initrd_filename, const char *cpu_model)
> -{
> - sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
> - kernel_cmdline, initrd_filename, cpu_model);
> -}
> -
> -/* SPARCstation Voyager hardware initialisation */
> -static void vger_init(ram_addr_t RAM_size,
> - const char *boot_device,
> - const char *kernel_filename, const char
> *kernel_cmdline,
> - const char *initrd_filename, const char *cpu_model)
> -{
> - sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
> - kernel_cmdline, initrd_filename, cpu_model);
> -}
> -
> -/* SPARCstation LX hardware initialisation */
> -static void ss_lx_init(ram_addr_t RAM_size,
> - const char *boot_device,
> - const char *kernel_filename, const char
> *kernel_cmdline,
> - const char *initrd_filename, const char *cpu_model)
> -{
> - sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
> - kernel_cmdline, initrd_filename, cpu_model);
> -}
> -
> -/* SPARCstation 4 hardware initialisation */
> -static void ss4_init(ram_addr_t RAM_size,
> - const char *boot_device,
> - const char *kernel_filename, const char *kernel_cmdline,
> - const char *initrd_filename, const char *cpu_model)
> -{
> - sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
> - kernel_cmdline, initrd_filename, cpu_model);
> -}
> -
> -/* SPARCClassic hardware initialisation */
> -static void scls_init(ram_addr_t RAM_size,
> - const char *boot_device,
> - const char *kernel_filename, const char
> *kernel_cmdline,
> - const char *initrd_filename, const char *cpu_model)
> -{
> - sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
> - kernel_cmdline, initrd_filename, cpu_model);
> -}
> -
> -/* SPARCbook hardware initialisation */
> -static void sbook_init(ram_addr_t RAM_size,
> - const char *boot_device,
> - const char *kernel_filename, const char
> *kernel_cmdline,
> - const char *initrd_filename, const char *cpu_model)
> -{
> - sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
> - kernel_cmdline, initrd_filename, cpu_model);
> -}
> -
> -static QEMUMachine ss5_machine = {
> - .name = "SS-5",
> - .desc = "Sun4m platform, SPARCstation 5",
> - .init = ss5_init,
> - .use_scsi = 1,
> - .is_default = 1,
> -};
> -
> -static QEMUMachine ss10_machine = {
> - .name = "SS-10",
> - .desc = "Sun4m platform, SPARCstation 10",
> - .init = ss10_init,
> - .use_scsi = 1,
> - .max_cpus = 4,
> -};
> -
> -static QEMUMachine ss600mp_machine = {
> - .name = "SS-600MP",
> - .desc = "Sun4m platform, SPARCserver 600MP",
> - .init = ss600mp_init,
> - .use_scsi = 1,
> - .max_cpus = 4,
> -};
> -
> -static QEMUMachine ss20_machine = {
> - .name = "SS-20",
> - .desc = "Sun4m platform, SPARCstation 20",
> - .init = ss20_init,
> - .use_scsi = 1,
> - .max_cpus = 4,
> -};
> -
> -static QEMUMachine voyager_machine = {
> - .name = "Voyager",
> - .desc = "Sun4m platform, SPARCstation Voyager",
> - .init = vger_init,
> - .use_scsi = 1,
> -};
> -
> -static QEMUMachine ss_lx_machine = {
> - .name = "LX",
> - .desc = "Sun4m platform, SPARCstation LX",
> - .init = ss_lx_init,
> - .use_scsi = 1,
> -};
> -
> -static QEMUMachine ss4_machine = {
> - .name = "SS-4",
> - .desc = "Sun4m platform, SPARCstation 4",
> - .init = ss4_init,
> - .use_scsi = 1,
> -};
> -
> -static QEMUMachine scls_machine = {
> - .name = "SPARCClassic",
> - .desc = "Sun4m platform, SPARCClassic",
> - .init = scls_init,
> - .use_scsi = 1,
> -};
> -
> -static QEMUMachine sbook_machine = {
> - .name = "SPARCbook",
> - .desc = "Sun4m platform, SPARCbook",
> - .init = sbook_init,
> - .use_scsi = 1,
> -};
> -
> -static const struct sun4d_hwdef sun4d_hwdefs[] = {
> - /* SS-1000 */
> - {
> - .iounit_bases = {
> - 0xfe0200000ULL,
> - 0xfe1200000ULL,
> - 0xfe2200000ULL,
> - 0xfe3200000ULL,
> - -1,
> - },
> - .tcx_base = 0x820000000ULL,
> - .slavio_base = 0xf00000000ULL,
> - .ms_kb_base = 0xf00240000ULL,
> - .serial_base = 0xf00200000ULL,
> - .nvram_base = 0xf00280000ULL,
> - .counter_base = 0xf00300000ULL,
> - .espdma_base = 0x800081000ULL,
> - .esp_base = 0x800080000ULL,
> - .ledma_base = 0x800040000ULL,
> - .le_base = 0x800060000ULL,
> - .sbi_base = 0xf02800000ULL,
> - .nvram_machine_id = 0x80,
> - .machine_id = ss1000_id,
> - .iounit_version = 0x03000000,
> - .max_mem = 0xf00000000ULL,
> - .default_cpu_model = "TI SuperSparc II",
> - },
> - /* SS-2000 */
> - {
> - .iounit_bases = {
> - 0xfe0200000ULL,
> - 0xfe1200000ULL,
> - 0xfe2200000ULL,
> - 0xfe3200000ULL,
> - 0xfe4200000ULL,
> - },
> - .tcx_base = 0x820000000ULL,
> - .slavio_base = 0xf00000000ULL,
> - .ms_kb_base = 0xf00240000ULL,
> - .serial_base = 0xf00200000ULL,
> - .nvram_base = 0xf00280000ULL,
> - .counter_base = 0xf00300000ULL,
> - .espdma_base = 0x800081000ULL,
> - .esp_base = 0x800080000ULL,
> - .ledma_base = 0x800040000ULL,
> - .le_base = 0x800060000ULL,
> - .sbi_base = 0xf02800000ULL,
> - .nvram_machine_id = 0x80,
> - .machine_id = ss2000_id,
> - .iounit_version = 0x03000000,
> - .max_mem = 0xf00000000ULL,
> - .default_cpu_model = "TI SuperSparc II",
> - },
> -};
> -
> static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
> {
> DeviceState *dev;
> @@ -1599,6 +1541,8 @@ static void sun4d_hw_init(const struct sun4d_hwdef
> *hwdef, ram_addr_t RAM_size,
> qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
> }
>
> +static struct sun4d_hwdef sun4d_hwdefs[];
> +
> /* SPARCserver 1000 hardware initialisation */
> static void ss1000_init(ram_addr_t RAM_size,
> const char *boot_device,
> @@ -1619,42 +1563,72 @@ static void ss2000_init(ram_addr_t RAM_size,
> kernel_cmdline, initrd_filename, cpu_model);
> }
>
> -static QEMUMachine ss1000_machine = {
> - .name = "SS-1000",
> - .desc = "Sun4d platform, SPARCserver 1000",
> - .init = ss1000_init,
> - .use_scsi = 1,
> - .max_cpus = 8,
> -};
> -
> -static QEMUMachine ss2000_machine = {
> - .name = "SS-2000",
> - .desc = "Sun4d platform, SPARCcenter 2000",
> - .init = ss2000_init,
> - .use_scsi = 1,
> - .max_cpus = 20,
> -};
> -
> -static const struct sun4c_hwdef sun4c_hwdefs[] = {
> - /* SS-2 */
> +static struct sun4d_hwdef sun4d_hwdefs[] = {
> + /* SS-1000 */
> {
> - .iommu_base = 0xf8000000,
> - .tcx_base = 0xfe000000,
> - .slavio_base = 0xf6000000,
> - .intctl_base = 0xf5000000,
> - .counter_base = 0xf3000000,
> - .ms_kb_base = 0xf0000000,
> - .serial_base = 0xf1000000,
> - .nvram_base = 0xf2000000,
> - .fd_base = 0xf7200000,
> - .dma_base = 0xf8400000,
> - .esp_base = 0xf8800000,
> - .le_base = 0xf8c00000,
> - .aux1_base = 0xf7400003,
> - .nvram_machine_id = 0x55,
> - .machine_id = ss2_id,
> - .max_mem = 0x10000000,
> - .default_cpu_model = "Cypress CY7C601",
> + .machine = {
> + .name = "SS-1000",
> + .desc = "Sun4d platform, SPARCserver 1000",
> + .init = ss1000_init,
> + .use_scsi = 1,
> + .max_cpus = 8,
> + },
> + .iounit_bases = {
> + 0xfe0200000ULL,
> + 0xfe1200000ULL,
> + 0xfe2200000ULL,
> + 0xfe3200000ULL,
> + -1,
> + },
> + .tcx_base = 0x820000000ULL,
> + .slavio_base = 0xf00000000ULL,
> + .ms_kb_base = 0xf00240000ULL,
> + .serial_base = 0xf00200000ULL,
> + .nvram_base = 0xf00280000ULL,
> + .counter_base = 0xf00300000ULL,
> + .espdma_base = 0x800081000ULL,
> + .esp_base = 0x800080000ULL,
> + .ledma_base = 0x800040000ULL,
> + .le_base = 0x800060000ULL,
> + .sbi_base = 0xf02800000ULL,
> + .nvram_machine_id = 0x80,
> + .machine_id = ss1000_id,
> + .iounit_version = 0x03000000,
> + .max_mem = 0xf00000000ULL,
> + .default_cpu_model = "TI SuperSparc II",
> + },
> + /* SS-2000 */
> + {
> + .machine = {
> + .name = "SS-2000",
> + .desc = "Sun4d platform, SPARCcenter 2000",
> + .init = ss2000_init,
> + .use_scsi = 1,
> + .max_cpus = 20,
> + },
> + .iounit_bases = {
> + 0xfe0200000ULL,
> + 0xfe1200000ULL,
> + 0xfe2200000ULL,
> + 0xfe3200000ULL,
> + 0xfe4200000ULL,
> + },
> + .tcx_base = 0x820000000ULL,
> + .slavio_base = 0xf00000000ULL,
> + .ms_kb_base = 0xf00240000ULL,
> + .serial_base = 0xf00200000ULL,
> + .nvram_base = 0xf00280000ULL,
> + .counter_base = 0xf00300000ULL,
> + .espdma_base = 0x800081000ULL,
> + .esp_base = 0x800080000ULL,
> + .ledma_base = 0x800040000ULL,
> + .le_base = 0x800060000ULL,
> + .sbi_base = 0xf02800000ULL,
> + .nvram_machine_id = 0x80,
> + .machine_id = ss2000_id,
> + .iounit_version = 0x03000000,
> + .max_mem = 0xf00000000ULL,
> + .default_cpu_model = "TI SuperSparc II",
> },
> };
>
> @@ -1791,6 +1765,8 @@ static void sun4c_hw_init(const struct sun4c_hwdef
> *hwdef, ram_addr_t RAM_size,
> qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
> }
>
> +static struct sun4c_hwdef sun4c_hwdefs[];
> +
> /* SPARCstation 2 hardware initialisation */
> static void ss2_init(ram_addr_t RAM_size,
> const char *boot_device,
> @@ -1801,27 +1777,49 @@ static void ss2_init(ram_addr_t RAM_size,
> kernel_cmdline, initrd_filename, cpu_model);
> }
>
> -static QEMUMachine ss2_machine = {
> - .name = "SS-2",
> - .desc = "Sun4c platform, SPARCstation 2",
> - .init = ss2_init,
> - .use_scsi = 1,
> +static struct sun4c_hwdef sun4c_hwdefs[] = {
> + /* SS-2 */
> + {
> + .machine = {
> + .name = "SS-2",
> + .desc = "Sun4c platform, SPARCstation 2",
> + .init = ss2_init,
> + .use_scsi = 1,
> + },
> + .iommu_base = 0xf8000000,
> + .tcx_base = 0xfe000000,
> + .slavio_base = 0xf6000000,
> + .intctl_base = 0xf5000000,
> + .counter_base = 0xf3000000,
> + .ms_kb_base = 0xf0000000,
> + .serial_base = 0xf1000000,
> + .nvram_base = 0xf2000000,
> + .fd_base = 0xf7200000,
> + .dma_base = 0xf8400000,
> + .esp_base = 0xf8800000,
> + .le_base = 0xf8c00000,
> + .aux1_base = 0xf7400003,
> + .nvram_machine_id = 0x55,
> + .machine_id = ss2_id,
> + .max_mem = 0x10000000,
> + .default_cpu_model = "Cypress CY7C601",
> + },
> };
>
> static void ss2_machine_init(void)
> {
> - qemu_register_machine(&ss5_machine);
> - qemu_register_machine(&ss10_machine);
> - qemu_register_machine(&ss600mp_machine);
> - qemu_register_machine(&ss20_machine);
> - qemu_register_machine(&voyager_machine);
> - qemu_register_machine(&ss_lx_machine);
> - qemu_register_machine(&ss4_machine);
> - qemu_register_machine(&scls_machine);
> - qemu_register_machine(&sbook_machine);
> - qemu_register_machine(&ss1000_machine);
> - qemu_register_machine(&ss2000_machine);
> - qemu_register_machine(&ss2_machine);
> + int i;
> + for (i = 0; i < ARRAY_SIZE(sun4m_hwdefs); i++) {
> + qemu_register_machine(&sun4m_hwdefs[i].machine);
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(sun4d_hwdefs); i++) {
> + qemu_register_machine(&sun4d_hwdefs[i].machine);
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(sun4c_hwdefs); i++) {
> + qemu_register_machine(&sun4c_hwdefs[i].machine);
> + }
> }
>
> machine_init(ss2_machine_init);
> --
> 1.7.1
>
>
[Qemu-devel] [PATCH v2 4/5] hw/sun4m: Use the QEMUMachine max_ram to implement memory limit, Peter Maydell, 2011/03/28
[Qemu-devel] Re: [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct, Blue Swirl, 2011/03/28