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[Qemu-devel] [Bug 757702] Re: Undefined instruction exception starts at
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [Bug 757702] Re: Undefined instruction exception starts at offset 0x8 instead of 0x4 |
Date: |
Tue, 12 Apr 2011 09:29:49 -0000 |
** Attachment added: "test program (source)"
https://bugs.launchpad.net/qemu/+bug/757702/+attachment/2023202/+files/undef-exc.s
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https://bugs.launchpad.net/bugs/757702
Title:
Undefined instruction exception starts at offset 0x8 instead of 0x4
Status in QEMU:
New
Bug description:
ARMv7a has lot of undefined instruction from its instruction opcode
space. This undefined instructions are very useful for replacing
sensitive non-priviledged instructions of guest operating systems
(virtualization). The undefined instruction exception executes at
<exception_base> + 0x4, where <exception_base> can be 0x0 or
0xfff00000. Currently, in qemu 0.14.0 undefined instruction fault at
0x8 offset instead of 0x4. This was not a problem with qemu 0.13.0,
seems like this is a new bug. As as example, if we try to execute
value "0xec019800" in qemu 0.14.0 then it should cause undefined
exception at <exception_base>+0x4 since "0xec019800" is an undefined
instruction.
- [Qemu-devel] [PATCH 0/5] PPC: Add FSL (e500) MMU emulation, Alexander Graf, 2011/04/30
- [Qemu-devel] [PATCH 1/5] PPC: Make MPC8544DS obey -cpu switch, Alexander Graf, 2011/04/30
- [Qemu-devel] [PATCH 3/5] PPC: Add GS MSR definition, Alexander Graf, 2011/04/30
- [Qemu-devel] [PATCH 2/5] PPC: Make MPC8544DS emulation work w/o KVM, Alexander Graf, 2011/04/30
- [Qemu-devel] [PATCH 4/5] PPC: Add another 64 bits to instruction feature mask, Alexander Graf, 2011/04/30
- [Qemu-devel] [PATCH 5/5] PPC: Implement e500 (FSL) MMU, Alexander Graf, 2011/04/30