[Qemu-devel] Model of simple Bus Mastering ADC for QEMU

[wzab]

Hi All,

I'm interested in using of QEMU as a simple environment providing
virtual hardware for my students, learning how to write device
drivers for different devices.
Unfortunately the QEMU's API seems to be not very strictly documented :-(.

I've tried to implement a simple Analog to Digital Converter model,
connected directly to the PC system bus (at 0x41000000 physical address)
and using the IRQ 5 line via standard ISA PIC.
The ADC is able to take control over the system bus and write the data 
into the system RAM, after the physical address of allocated RAM is 
written by the driver to proper registers (one register per page).

I'd appreciate any remarks regarding my implementation.
The model is working, but I don't know if I have correctly used
functionalities of QEMU.

Next step should be to extend the model with the PCI interface...

BTW. Is it possible to write similar models for devices connected
via SPI interface to the embedded system?

If you are interested, you can find my sources (model, Linux driver
anmd sample program using it) in the alt.sources usenet group, as a 
message with subject:
"Model of Bus Mastering ADC implemented in QEMU" or message
<address@hidden>
or simply in the Google archive:
http://groups.google.com/group/alt.sources/msg/4592a94e584b85a6

--
Best Regards,
Wojtek Zabolotny