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Re: [Qemu-devel] TCG: AREG0 removal planning
From: |
Blue Swirl |
Subject: |
Re: [Qemu-devel] TCG: AREG0 removal planning |
Date: |
Wed, 11 May 2011 20:35:47 +0300 |
On Wed, May 11, 2011 at 1:57 AM, Paul Brook <address@hidden> wrote:
>> While we're at it, let us change things a bit further to allow guest
>> byte-swap load/store insns to be implemented more efficiently. For
>> instance, currently a sparc load_asr (little-endian), as emulated on
>> an x86 host, does the byte swap twice.
>
> FWIW this also ends up interacting with the device and bus models. This is
> partially implemented by the endian parameter of cpu_register_io_memory et.
> al. This may also be a runtime property, either part of the CPU state (e.g.
> ARM where instruction and data accesses may have different endianness), or
> even a per-page TLB attribute (PPC?).
SuperSparc (Sparc32) MMU had a bit for reversing the endianness of a
page, on Sparc64 there are many levels where this can be done (global
CPU mode flag, MMU page flag and some memory accesses can use byte
swapping ASIs). I don't think they are used though.
- Re: [Qemu-devel] TCG: AREG0 removal planning, (continued)
Re: [Qemu-devel] TCG: AREG0 removal planning, Stefan Weil, 2011/05/10
Re: [Qemu-devel] TCG: AREG0 removal planning, Richard Henderson, 2011/05/10