Re: [Qemu-devel] [PATCH RFC 00/11] AREG0 elimination

[Aurelien Jarno]

On Sun, May 15, 2011 at 03:37:00PM +0300, Blue Swirl wrote:
> On Sun, May 15, 2011 at 3:14 PM, Laurent Desnogues
> <address@hidden> wrote:
> > On Sun, May 15, 2011 at 1:33 PM, Blue Swirl <address@hidden> wrote:
> > [...]
> >>> x86_64 uses r14 as TCG_AREG0. Despite the instructions being quite
> >>> simple (only 2 movi_i32), the resulting code makes 2 access to env to
> >>> save the two registers. Having to reload the env pointer each time to a
> >>> register would clearly increase the size of this TB.
> >>
> >> I don't think TCG would be that simple, instead the pointer would be
> >> loaded only once in this case.
> >
> > Assuming TCG was able to allocate a register for that,
> > it would be live at most for one TB, so you'd have to
> > load it at least once per TB, and with block chaining
> > that wouldn't be efficient as you'd keep on reloading it.
> 
> Yes, but if there are better uses, the register can be flushed. Now
> this is not possible since the register is always unavailable.
> 

What are the better uses, that justify to flush a register that is going
to be used three or four host asm later? 

In the current generated code, roughly one every four instruction
reference TCG_AREG0, so this register is really needed very often.

If you think TCG will be faster by having one more register in between
I suggest you to first optimize tcg_reg_alloc(), which simply spill
a random register, even if they are some allocated register that won't
be used until the end of the TB. You should also should check how often
TCG spills a register (in which case it would have benefit from one more
register). It happens less than 2000 times when booting an emulated mips
system on x86_64, while more than 160000 TB are generated.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net