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[Qemu-devel] [PATCH 17/26] target-xtensa: implement RST2 group (32 bit m
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 17/26] target-xtensa: implement RST2 group (32 bit mul/div/rem) |
Date: |
Wed, 18 May 2011 02:32:43 +0400 |
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/translate.c | 60 ++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 59 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 7deda1b..8933e5a 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -854,7 +854,65 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 2: /*RST2*/
- TBD();
+ if (_OP2 >= 12) {
+ HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
+ int label = gen_new_label();
+ tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
+ gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
+ gen_set_label(label);
+ }
+
+ switch (_OP2) {
+ case 8: /*MULLi*/
+ HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
+ tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ case 10: /*MULUHi*/
+ case 11: /*MULSHi*/
+ HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
+ {
+ TCGv_i64 r = tcg_temp_new_i64();
+ TCGv_i64 s = tcg_temp_new_i64();
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ if (_OP2 == 10) {
+ tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
+ tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
+ } else {
+ tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
+ tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
+ }
+ tcg_gen_mul_i64(r, s, t);
+ tcg_gen_shri_i64(r, r, 32);
+ tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
+
+ tcg_temp_free_i64(r);
+ tcg_temp_free_i64(s);
+ tcg_temp_free_i64(t);
+ }
+ break;
+
+ case 12: /*QUOUi*/
+ tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ case 13: /*QUOSi*/
+ tcg_gen_div_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ case 14: /*REMUi*/
+ tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ case 15: /*REMSi*/
+ tcg_gen_rem_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+ }
break;
case 3: /*RST3*/
--
1.7.3.4
- Re: [Qemu-devel] [PATCH 09/26] target-xtensa: add special and user registers, (continued)
[Qemu-devel] [PATCH 10/26] target-xtensa: implement RST3 group, Max Filippov, 2011/05/17
[Qemu-devel] [PATCH 11/26] target-xtensa: implement shifts (ST1 and RST1 groups), Max Filippov, 2011/05/17
[Qemu-devel] [PATCH 12/26] target-xtensa: implement LSAI group, Max Filippov, 2011/05/17
[Qemu-devel] [PATCH 13/26] target-xtensa: mark reserved and TBD opcodes, Max Filippov, 2011/05/17
[Qemu-devel] [PATCH 14/26] target-xtensa: implement SYNC group, Max Filippov, 2011/05/17
[Qemu-devel] [PATCH 15/26] target-xtensa: implement CACHE group, Max Filippov, 2011/05/17
[Qemu-devel] [PATCH 16/26] target-xtensa: implement exceptions, Max Filippov, 2011/05/17
[Qemu-devel] [PATCH 17/26] target-xtensa: implement RST2 group (32 bit mul/div/rem),
Max Filippov <=
[Qemu-devel] [PATCH 18/26] target-xtensa: implement windowed registers, Max Filippov, 2011/05/17
[Qemu-devel] [PATCH 19/26] target-xtensa: implement loop option, Max Filippov, 2011/05/17
[Qemu-devel] [PATCH 20/26] target-xtensa: implement extended L32R, Max Filippov, 2011/05/17