[Qemu-devel] [PATCH] ppc64: fix mtmsr behavior on 64-bit targets

[Nathan Whitehorn]

The mtmsr instruction is required not to modify the upper 32-bits of the 
machine state register, but checks the current value of MSR[SF] to 
decide whether to do this. This has the effect of zeroing the upper 32 
bits of the MSR whenever mtmsr is executed in 64-bit mode. 
Unconditionally preserve the upper 32-bits in mtmsr for TARGET_PPC64.

---
 target-ppc/translate.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 9b3f90c..a60dbe9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3886,7 +3886,6 @@ static void gen_mtmsr(DisasContext *ctx)
          */
         gen_update_nip(ctx, ctx->nip);
 #if defined(TARGET_PPC64)
-        if (!ctx->sf_mode) {
             TCGv t0 = tcg_temp_new();
             TCGv t1 = tcg_temp_new();
             tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
@@ -3895,9 +3894,9 @@ static void gen_mtmsr(DisasContext *ctx)
             tcg_temp_free(t1);
             gen_helper_store_msr(t0);
             tcg_temp_free(t0);
-        } else
-#endif
+#else
             gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
+#endif
         /* Must stop the translation as machine state (may have) 
changed */
         /* Note that mtmsr is not always defined as 
context-synchronizing */
         gen_stop_exception(ctx);